Logarithmic and exponential converter circuits

A logarithmic amplifier comprising:

• first and second mirror circuits, each comprising an active transistor, a cascode transistor, and a base current compensating transistor, the cascode and active transistors being connected in series between a reference current input node connected to the cascode transistor and a reference potential connected to the active transistor, a base of the cascode transistor being connected to a bias voltage, and the base current compensating transistor being connected between a supply voltage source and a base of the active transistor, a base of the base current compensating transistor being connected to the reference current input node;
• a resistor connected between the cascode and active transistors of the first and second mirror circuits;
• third and fourth mirror circuits each comprising:
• a mirror cascode transistor connected between a current input node and a floating output node, and having a base connected to the base of a respective one of said cascode transistors of said first and second mirror circuits;
• a mirror base current compensating transistor connected between the supply voltage source and the base of the mirror cascode transistor, and having a base connected to the current input node;
• wherein the floating output nodes of said third and fourth mirror circuits are interconnected;
• a diode connected transistor connected between the floating output nodes of the third and fourth mirror circuits and the reference potential;
• and first and second output circuits for developing first and second output signals in response to a current flowing of one of said active transistors;
• whereby when an input current is applied between the input node and the supply voltage source of one of the third mirror circuit, and reference currents applied between input nodes and the supply voltage source of the first, second, and fourth mirror circuits, the first output signal has a logarithmic relationship to the input current.

An exponential converter comprising:

• a first mirror circuit, comprising an active transistor, a cascode transistor, and a base current compensating transistor, the cascode and active transistors being connected in series between a reference current input node connected to the cascode transistor and a reference potential connected to the active transistor, and the base current compensating transistor being connected between a supply voltage source and a base of the active transistor, a base of the base current compensating transistor being connected to the reference current input node;
• a second mirror circuit, comprising an active transistor, a cascode transistor, and a base current compensating transistor, the cascode and active transistors being connected in series between a reference current input node connected to the cascode transistor and the reference potential connected to the active transistor, and the base current compensating transistor being connected between a supply voltage source and a base of the cascode transistor, a base of the base current compensating transistor being connected to the reference current input node;
• the bases of the active transistors of the first and second mirror circuits being interconnected;
• and a resistor connected from nodes the cascode and active transistors of the first and second mirror circuits;
• and
• an output circuit comprising:
• a third mirror circuit, comprising an active transistor, a cascode transistor, and a base current compensating transistor, the cascode and active transistors being connected in series between a reference current input node connected to the cascode transistor and a reference potential connected to the active transistor, and the base current compensating transistor being connected between a supply voltage source and a base of the cascode transistor, a base of the base current compensating transistor being connected to the reference current input node, the base of the cascode transistor being connected to a base of the cascode transistor of the first mirror circuit, and the base of the active transistor being connected to a node between the cascode transistor and the active transistor;
• and
• an output transistor connected between an output node and the node between the cascode transistor and the active transistor, a base of the output transistor being connected to the base of the cascode transistor of the second mirror circuit;
• whereby when a first differential input current is applied from the node between the cascode and active transistors of the first mirror circuit and the reference potential, a second differential input current is applied from the node between the cascode and active transistors of the second mirror circuit and the reference potential, and reference currents are applied to the reference current input nodes of the first and second mirror circuits with respect to the supply voltage source, an output signal at the circuit output node is developed as an exponential function of the input currents.