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US 5,471,094 AGranted
Self-aligned via structure
AssigneeIntegrated Device Technology, Inc.
InventorChuen-Der Lien
Life of this patent
Estimating the term…
Abstract
A self-aligned via between interconnect layers in an integrated circuit allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density and improved yield. In one embodiment, self-aligned vias are used to connect first and second interconnect layers in an SRAM memory cell.
Claims5
A self-aligned via structure, comprising:
- a semiconductor substrate;
- a polysilicon first interconnect layer overlying one surface of said substrate, a portion of said first interconnect layer forming a gate of a metal oxide semiconductor field effect transistor;
- a first dielectric layer formed directly upon said first interconnect layer, said first dielectric layer having upper and lower surfaces and having an opening extending between said upper and lower surfaces, and said first dielectric layer having at least one edge aligned with one edge of said first interconnect layer;
- a polysilicon conductive plug formed within said opening, said conductive plug having an upper surface and having a lower surface contacting the upper surface of said first interconnect layer, and said conductive plug having at least one edge aligned with one edge of said first interconnect layer;
- and
- a second dielectric layer overlying said substrate surface, and overlying at least one edge of said first dielectric layer, at least one edge of said first interconnect layer, and at least one edge of said conductive plug, but not overlying the upper surface of said conductive plug.
3 more elements
Dependencies are inferred from the claim text.