Techniques for via formation and filling
AssigneeLSI Logic Corporation
InventorsNicholas F. Pasch, Roger Patrick
Life of this patent
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Abstract
Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.
Claims5
A semiconductor device, comprising:
- a substrate;
- a first structure-containing layer, overlying the substrate, containing first structures requiring inter-connection through first subsequently formed vias from a higher level;
- a first insulating layer overlying the first structure-containing layer;
- a second structure-containing layer overlying the first insulating layer, disposed at a higher level than the first structure-containing layer, and containing second structures requiring inter-connection through second subsequently formed vias from the higher level;
- a second insulating layer overlying the second structure-containing layer;
- and
- planarized metal filling the second and first vias and making contact from the higher level to the second and first structures, respectively;
- wherein:
- the second vias are shallow vias formed through the second insulating layer to the second structures;
- the first vias are deep vias formed through the second insulating layer and through the first insulating layer to the first structures;
- and
- any excess metal initially over-filling the vias is subsequently removed by polishing.
Dependencies are inferred from the claim text.