Electronic structures having a joining geometry providing reduced capacitive loading

Abstract

Electrical interconnection structures are described. The electrical interconnection structures are formed by electrically interconnecting in a stack a plurality of discrete substrates. By using a plurality of discrete substrates, a multilayer dielectric/electrical conductor structure can be fabricated from individual discrete substrates each of which can be tested prior to forming a composite stack so that defects in each discrete substrate can be eliminated before inclusion into the stack. Electrical interconnection between adjacent substrate is provided by an array of contact locations on each surface of the adjacent substrates. Corresponding contacts on adjacent substrates are adapted for mutual electrical engagement. Adjacent contact locations can be thermocompression bonded. To reduce the parasitic capacitance and coupled noise between the contact pads and the electrical conductors within the interior of each discrete substrate, the contact pads on each substrate have elongated shape. The elongated contact pads or lattice pads on adjacent substrates are nonparallel and preferably orthogonal so that the corresponding pads of adjacent substrates electrically interconnect an intersecting area which varies in location along the elongated contact pads as the placement of the adjacent substrates varies in the manufacture.

Dependencies are inferred from the claim text.