An electronic data memory containing an array of cells wherein all such cells each have one connection to a conductive nominal column, and one connection to each of a pair of conductive nominal rows, each cell comprising:
- (a) a capacitor, a first plate of which is connected to the conductive column;
- (b) a first columnar stack of semiconductive doped regions fabricated without detail specification across the cross-section of the column except for column surrounding insulation where required, where one end of the column is connected to the first row of the pair, and where the other end of the column is connected to a second plate of the capacitor, where one or more semiconductive doped regions may be connected laterally through the sides of the column to adjacent like regions as part of a continuing trace;
- (c) a second columnar stack of semiconductive doped regions fabricated without detail specification across the cross-section of the column except for column surrounding insulation where required, where one end of the column is connected to the second plate of the capacitor, and where the other end of the column is connected to the second row of the pair, where one or more semiconductive doped regions may be connected laterally through the sides of the column to adjacent like regions as part of a continuing trace;
- (d) the columns of the array each being controlled by a drive circuit which causes charge to be conducted to and from cells in the array;
- (e) the first row of each row pair being connected to a drive circuit which causes charge to be conducted to cells of the array;
- (f) a discharge drive circuit connected to the other row of each row pair which causes charge to be conducted away from the cells of the array;
- (g) sensing circuits which can sense differences in the amount of charge either charging or discharging the cells in the array;
- (h) wherein selection of a given column and charging row or rows causes the capacitor or capacitors of the selected cell or cells at the column-row intersection or intersections to be selectively charged;
- (i) wherein the selection of a given column and a given discharging row or rows causes the capacitor or capacitors of a selected cell or cells in the array to be selectively discharged or reverse charged;
- (j) where the discharge and/or charge voltage or voltages, or current or currents, can be selectively sensed so as to ascertain charge status of a selected cell's capacitor;
- (k) status result of that sensing or those sensings being made available outside the aforementioned memory circuit;
- (l) wherein groups of columns in the array are formed by columnar shaped monolithic integrated circuit dice, and wherein interconnections which allow continuation of rows and columns between monolithic dice are formed from added circuit jumper traces by deposition and etching of material which forms or materials which form isolated conductive links, these links forming interconnections between adjacent traces of the dice;
- (m) wherein fault regions within the array are excised by removal of conductive column material above and below a faulty cell or cells in a row or group of rows, and wherein conductive material at or between ends of a faulty row or rows is excised to isolate the faulty cell or cells between the column excise points and the row excise points;
- (n) wherein row traces leading to and from excised rows are interconnected to bypass traces by melting and joining overlapping conductors to form electrical interconnections which create each bypass.