US 5,471,081 AGranted

Semiconductor device with reduced time-dependent dielectric failures

AssigneeDigital Equipment Corporation

InventorsBruce J. Fishbein, Brian S. Doyle

Life of this patent

Estimating the term…

Loading patent…

Abstract

An insulated gate field-effect transistor or similar semiconductor-insulator-semiconductor structure has an increased time-dependent dielectric failure lifetime due to a reduction in the field across the gate insulator. The electric field in the gate insulator is reduced without degrading device performance by limiting the field only when the gate voltage exceeds its nominal range. The field is limited by lowering the impurity concentration in a polysilicon gate electrode so that the voltage drop across the gate insulator is reduced. In order to avoid degrading the device performance when the device is operating with nominal voltage levels, a fixed charge is imposed at the interface between the gate electrode and the gate insulator, so at a gate voltage of about the supply voltage level the response changes to exhibit less increase in the drop across the gate insulator for higher voltages. Also, the impurity level in the gate electrode may be low enough so that the gate is in deep depletion for transient increases in gate voltage, thereby limiting the drop across the gate insulator.

Claims5

Dependent claims

A method of operating a semiconductor device, said semiconductor device including:

a substrate composed of silicon semiconductor material and having a surface-adjacent region at a face of said substrate;
an insulating layer on said face composed of silicon oxide overlying said surface-adjacent region of the substrate;
an electrode on said face overlying said insulating layer above said surface adjacent region, said electrode being composed of polysilicon semiconductor material doped with impurities, wherein said electrode is a gate of a field-effect transistor or plate of a field-effect capacitor;
comprising the steps of:
a) applying a first bias voltage to said electrode with respect to said face, said first bias voltage being substantially above a substrate inversion threshold voltage for said semiconductor device but below a selected level, and wherein said selected level is about that of a voltage supply for said semiconductor device, to produce a voltage across said insulating layer of approximately said applied first bias voltage, said first bias voltage being applied after a positive fixed charge is provided at the interface of said insulating layer and said electrode, said positive fixed charge preventing said first bias voltage from causing depletion in said electrode;
and
b) applying a second bias voltage to said electrode with respect to said face, said second bias voltage being above said selected level, to produce a voltage across said insulating layer of substantially less than said second bias voltage,
said polysilicon semiconductor material being doped at a level not more that about 5.times.10.sup.18 /cm.sup.3 so that an inversion layer is created in said surface-adjacent region by said second bias voltage applied to said electrode.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/026,625Filed 4 Mar 1993 · continuation
Priority: 16 Apr 1990
Granted: 28 Nov 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 64/0134
On single crystalline silicon, e.g. chemical oxidation using a liquid: with a treatment, e.g. annealing, after the formation of the insulator and…
H10D 1/66
Capacitors having potential barriers: conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
H10D 62/834
Being Group IV materials, e.g. B-doped Si or undoped Ge: further characterised by the dopants
H10D 64/661
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor comprising a layer of…