Low dielectric constant insulation layer for integrated circuit structure and method of making same

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises:

• a) forming one or more lower solid insulation layers on said integrated circuit structure;
• b) forming over said one or more lower solid insulation layers a composite layer comprising one or more insulation materials selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, an organic polymer, and mixtures of same and one or more extractable materials selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide;
• c) removing said one or more extractable materials leaving a porous structure comprising said low dielectric constant insulation layer;
• and
• d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer;
• whereby said lower and upper solid insulation layers respectively prevent migration of impurities from said porous structure into said integrated circuit structure.

A process for forming a low dielectric constant insulation layer as a portion of an integrated circuit structure on a semiconductor wafer which comprises:

• a) forming on said semiconductor wafer an insulation layer consisting essentially of a mixture of silicon oxide, germanium oxide, and optionally one or more dopants;
• and
• b) thereafter further processing said insulation layer to form a porous structure therein by removing said germanium oxide from said insulation layer to reduce the dielectric constant of said insulation layer;
• to thereby form said low dielectric constant insulation layer.

A process for forming a low dielectric constant insulation layer as a portion of an integrated circuit structure on a semiconductor wafer which comprises:

• a) forming one or more lower solid insulation layers on said semiconductor wafer;
• b) forming a composite layer comprising a silicon oxide non-extractable insulation material and a germanium oxide extractable material;
• c) removing said germanium oxide extractable material leaving a porous structure comprising said silicon oxide non-extractable insulation material to form said low dielectric constant insulation layer;
• and
• d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer after said extraction step;
• whereby said lower and upper solid insulation layers respectively inhibit downward or upward migration of impurities from said porous structure into other portions of said integrated circuit structure.

A process for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer which comprises:

• a) forming one or more lower solid insulation layers on said integrated circuit structure;
• b) forming a composite layer comprising one or more non-extractable insulation materials selected from the group consisting of an oxide of silicon, silicon nitride, aluminum oxide, an organic polymer, and mixtures of same and one or more extractable materials selected from the group consisting of germanium oxide, germanium sulfide, and silicon sulfide;
• c) removing said one or more extractable materials leaving a porous structure comprising said one or more non-extractable insulation materials to form said low dielectric constant insulation layer;
• and
• d) forming one or more upper solid insulation layers over said low dielectric constant insulation layer after said extraction step;
• e) forming one or more contact openings in said one or more lower solid insulation layers, said low dielectric constant insulation layer, and said one or more upper solid insulation layers;
• f) filling said contact openings with conductive material;
• and
• g) forming a patterned metal layer over an upper surface of said one or more upper solid insulation layers.