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US 5,470,790 AGranted
Via hole profile and method of fabrication
AssigneeIntel Corporation
InventorsAlan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
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Abstract
A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
Claims15
A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of:
- forming a first conductive layer above said substrate;
- forming a second conductive layer on said first conductive layer;
- forming an insulating layer over said second conductive layer;
- forming a first opening through said insulating layer, and said second conductive layer;
- and
- forming a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer.
3 more elements
A process for forming an interconnection structure of an integrated circuit comprising the steps of:
- forming an interconnection;
- etching said interconnection a first time to form a first opening having a first width in said interconnection;
- and
- etching said interconnection a second time beneath said first opening such that said interconnection is etched laterally to form a second opening which extends laterally further into said interconnection than said first opening.
1 more element
Dependencies are inferred from the claim text.