Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors
AssigneeIntegrated Devices Technology, Inc.
InventorChuen-Der Lien
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Abstract
A BiCMOS process is provided for fabricating on the same semiconductor substrate three types of N-wells optimized respectively for (i) PMOS FETs requiring low P+/N-well capacitance; (ii) NPN bipolar transistors which do not require low collector-to-substrate capacitance and PMOS FETs which require latch-up immunity; and (iii) NPN bipolar transistors which require low collector-to-substrate capacitance.
Claims9
A method for fabricating a well of a first conductivity type in a lightly doped monocrystalline semiconductor wafer, the method comprising the steps of:
- introducing a first dopant of the first conductivity type from a surface of said lightly doped monocrystalline semiconductor wafer, into a first region along the surface of said lightly doped monocrystalline semiconductor wafer to achieve a first dopant concentration in said first region;
- introducing a second dopant of the first conductivity type from the surface of said lightly doped monocrystalline semiconductor wafer to form a second region of said first conductivity type above said first region, said second region achieving a second dopant concentration higher than said first dopant concentration;
- growing a lightly doped epitaxial layer over said surface of said lightly doped monocrystalline semiconductor wafer, such that said first and second regions become buried regions in said lightly dope monocrystalline semiconductor wafer;
- and
- introducing a third dopant of the first conductivity type from the surface of said lightly doped monocrystalline semiconductor wafer into said epitaxial layer to form a third region of said lightly doped monocrystalline semiconductor wafer above said buried regions.
A process for simultaneously fabricating three wells of the same conductivity type but different characteristics in the same monocrystalline semiconductor wafer, said process comprising the steps of:
- introducing a dopant of a first conductivity type from a surface of said semiconductor wafer to form first, second and third regions of said first conductivity type at said surface of said semiconductor wafer, said first, second and third regions being physically isolated from each other;
- introducing a dopant of said first conductivity type from said surface of said semiconductor wafer to form in said second and third regions, respectively, fourth and fifth regions of said first conductivity type;
- introducing a dopant of a second conductivity type to form a first set of isolation regions between said first, second and third regions of said first conductivity type;
- growing an epitaxial layer on said surface of said semiconductor wafer, such that said first, second, third, fourth, fifth regions of said first conductivity type, and said isolation regions of said second conductivity type become buried regions of said semiconductor wafer;
- and
- introducing a dopant of said first conductivity type from said surface of said semiconductor wafer into said epitaxial layer to form a sixth region, a seventh region and an eighth region of said first conductivity type, said sixth, seventh and eighth regions being located, respectively, above said first, fourth and fifth regions, wherein said fourth region is located between, but not enclosed by, said second and seventh regions and further wherein said fifth region is enclosed by said third and eighth regions.
Dependencies are inferred from the claim text.