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US 5,470,763 AGranted
Method for manufacturing thin film transistor with short hydrogen passivation time
AssigneeNEC Corporation
InventorKoji Hamada
Life of this patent
Estimating the term…
Abstract
In a method for manufacturing a thin film transistor, a polycrystalline silicon layer, a gate insulating layer, a gate electrode layer, a non-doped insulating layer, and a metal connections layer are formed on a substrate, and then, a hydrogen passivation is carried out. The non-doped insulating layer has a thickness of less than approximately 100 nm.
Claims13
A method for manufacturing a thin film transistor, comprising the steps of:
- forming a polycrystalline silicon layer on a substrate;
- forming a gate insulating layer on said polycrystalline silicon layer;
- forming a gate electrodes layer on said gate insulating layer;
- patterning said gate electrode layer and said gate insulating layer;
- introducing impurity ions into said polycrystalline silicon layer in self-alignment with said patterned gate electrode layer to create source and drain regions in said polycrystalline silicon layer;
- forming a non-doped insulating layer on said patterned gate electrode layer and said polycrystalline silicon layer, said non-doped insulating layer having a thickness of less than approximately 100 nm;
- patterning said non-doped insulating layer;
- forming a metal connection layer over said patterned non-doped insulating layer;
- and
- performing hydrogen passivation upon said polycrystalline silicon layer after said metal connection layer is formed.
7 more elements
A method for manufacturing a thin film transistor, comprising the steps of:
- forming a polycrystalline silicon layer on a substrate;
- forming a gate insulating layer on said polycrystalline silicon layer;
- forming a gate electrode layer on said gate insulating layer;
- patterning said gate electrode layer and said gate insulating layer;
- introducing impurity ions into said polycrystalline silicon layer in self-alignment with said patterned gate electrode layer to create source and drain regions in said polycrystalline silicon layer;
- forming a non-doped insulating layer on said patterned gate electrode layer and said polycrystalline silicon layer by an LPCVD, said non-doped insulating layer having a thickness of less than approximately 100 nm;
- patterning said non-doped insulating layer to form contact holes opened to said source and drain regions;
- forming a metal connection layer on said patterned non-doped insulating layer;
- and
- performing hydrogen passivation by plasma discharge upon said polycrystalline silicon layer after said metal connection layer is formed.
7 more elements
A method for manufacturing a thin film transistor, comprising the steps of:
- forming a polycrystalline silicon layer on a substrate;
- forming a gate insulating layer on said polycrystalline silicon layer;
- forming a gate electrode layer on said gate insulating layer;
- patterning said gate electrode layer and said gate insulating layer;
- introducing impurity ions into said polycrystalline silicon layer in self-alignment with said patterned gate electrode layer to create source and drain regions in said polycrystalline silicon layer;
- forming a non-doped insulating layer on said patterned gate electrode layer and said polycrystalline silicon layer by an LPCVD, said non-doped insulating layer having a thickness of less than approximately 100 nm;
- forming an impurity-doped BPSG layer on said non-doped insulating layer;
- patterning said non-doped insulating layer and said BPSG layer to form contact holes opened to said source and drain regions;
- forming a metal connection layer on said patterned BPSG layer and non-doped insulating layer;
- and
- performing hydrogen passivation by plasma discharge upon said polycrystalline silicon layer after said metal connection layer is formed.
8 more elements
Dependencies are inferred from the claim text.