Transparent testing of integrated circuits
AssigneeSofia Koloni, Ltd.
InventorMichael Nicolaidis
Life of this patent
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Abstract
To carry out a transparent test of integrated circuits, all of the state registers and input/output registers that determine the applications' execution context are included into circular scan paths having the output of the last stage connected to the input of the first stage. Before the test, the contents of the registers are shifted via the scan path into a RAM. After the test, the saved contents of the registers are reloaded from the RAM to the registers via the scan path.
Claims11
A method for testing a memory coupled to a data compactor, comprising the following steps:
- a) providing a transparent test sequence including a succession of read and write operations on each memory cell, such that the initial state of the memory cell is re-established at the end of the test sequence and wherein the results of a predetermined number of read operations are to be provided to the data compactor;
- b) supplying the data compactor with data or the complements thereof, that the test sequence would provide if the memory cell were faultless;
- c) storing the state of the data compactor corresponding to the supplied data;
- d) carrying out the test sequence to change the state of the data compactor if faults are detected in the memory;
- and
- e) comparing the state of the data compactor after carrying out the test sequence with the stored state.
A method for testing a memory coupled to a data compactor having first and second analysis modes such that, when the data compactor is provided in the first mode with a succession of values in a direct order and then, in the second mode, the data compactor is provided with the same succession of values in the reverse order, the initial state of the data compactor is re-established, which method comprises the following steps:
- a) providing a transparent test sequence including a succession of read and write operations on each memory cell, such that the initial state of the memory cell is re-established at the end of the test sequence and wherein the results of a predetermined number of read operations are to be provided to the data compactor;
- b) providing the data compactor with data, or the complements thereof, that the test sequence, executed in reverse order, would provide if the memory cell were faultless;
- c) toggling the data compactor between the first and second analysis modes;
- d) carrying out the test sequence to change the state of the data compactor if faults are detected in the memory;
- and
- e) comparing the state of the data compactor after carrying out the test sequence with its initial state.
Dependencies are inferred from the claim text.