US 5,469,396 AGranted

Apparatus and method determining the resistance of antifuses in an array

AssigneeActel Corporation

InventorAbdelshafy A. Eltoukhy

Life of this patent

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Abstract

An additional column (or row) track is provided in an antifuse based interconnect array containing circuit structures identical to the circuit structures in the remaining columns of the array, except that antifuse vias are filled with contact or via plugs. These plug antifuse substitutes are addressable in the same manner and by the same circuitry as the antifuses on the integrated circuit. The programmed antifuse is addressed, a test voltage is placed on the V.sub.pp input pin on the integrated circuit, and the current drawn by the antifuse is measured. The plug antifuse substitute is addressed, the test voltage is placed on the V.sub.pp input pin on the integrated circuit, and the current drawn by the plug antifuse substitute is measured. The resistance of the entire circuit path which includes the programmed antifuse is calculated using the test voltage and the measured antifuse current and the resistance of the entire circuit path which includes the plug antifuse substitute is calculated using the test voltage and the measured plug antifuse substitute current. The difference between the two resistance values is an accurate measure of the resistance of the programmed antifuse.

In an integrated circuit containing circuit structures including functional circuitry, interconnect conductors, antifuses for selectively connecting inputs and outputs of the functional circuitry to one another through the interconnect conductors, programming transistors for selectively placing a programming voltage potential across the antifuses through programming circuit paths, each of said programming circuit paths comprising at least one of said programming transistors, at least one of said interconnect conductors, a selected one of said antifuses, and at least one I/O pin of said integrated circuit, and addressing circuitry for turning on selected ones of the programming transistors to define said programming circuit paths, a method for determining the resistance of programmed ones of said antifuses comprising the steps of:

programming a selected antifuse by turning on said at least one of said programming transistors to create a programming circuit path having a programming circuit path resistance and by applying said programming voltage across said programming circuit path from said at least one I/O pin of said integrated circuit;
measuring a programming circuit current drawn by said programming circuit path while said programming voltage is being applied and calculating said programming circuit path resistance of said programming circuit path;
providing a reference circuit structure on said integrated circuit, said reference circuit structure containing reference circuit elements substantially identical to all circuit elements in said programming circuit path except that a metal via plug is used in place of said selected antifuse;
creating a reference circuit path through said reference circuit structure having a reference circuit path resistance and applying said programming voltage across said reference circuit path from said at least one I/O pin of said integrated circuit,
measuring a reference circuit current drawn by said reference circuit structure while said programming voltage is being applied and calculating said reference circuit path resistance of said reference circuit structure;
and
subtracting said programming circuit path resistance from said reference circuit path resistance.

4 more elements

Facts

Application

08/255,160Filed 7 Jun 1994

Granted

21 Nov 1995

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 29/027
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in fuses
G11C 17/18
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…
G11C 29/02
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: detection or location of defective…
G11C 29/50
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: marginal testing, e.g. race, voltage…

Abstract

Claims1