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AssigneesThe Board of Regents of the University of Washington, Samsung Electronics Co., Ltd.
InventorsThomas Alexander, Yongmin Kim, Hyunwook Park, Kil-Su Eo, Jing-Ming Jong
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The present invention provides a unified image and graphics processing system that provides both image and graphics processing at high speeds. The system includes a parallel vector processing unit, a graphics subsystem, a shared memory and a set of high-speed data buses for connecting all of the other components. Generally, the parallel vector processing unit includes a series of vector processors. Each processor includes a vector address generator for efficient generation of memory addresses for regular address sequences. In order to synchronize and control the vector processors' accesses to shared memory, the parallel vector processing unit includes shared memory access logic. The logic is incorporated into each vector processor. The graphics subsystem includes a series of polygon processors in a pipelined configuration. Each processor is connected in the pipeline by a first-in-first-out (FIFO) buffer for passing data results. Additionally, each polygon processor is connected to a local shared memory in which program instructions and data are stored. The graphics subsystem also includes a device addressing mechanism for identifying a destination device using a tagged address. The shared memory, the parallel vector processor and the graphics subsystem also incorporate an abbreviated addressing scheme, which reduces the amount of information required to request sequential addresses from the shared memory.
A method of generating a device identification for data to be transmitted between a processor having an addressable memory space and one of a plurality of destination devices, the method comprising:
A method of generating a destination device for use in transferring bytes of graphics data from a processor for generating the bytes of graphics data to a plurality of destination devices for additional processing of the bytes of graphics data such that the processor is shared by the destination devices and selectively provides bytes of graphics data to each, such processor having a multibit data output and a separate multibit address output, which method comprises:
Dependencies are inferred from the claim text.