High speed digital parallel multiplier
AssigneeFujitsu Limited
InventorGensuke Goto
Life of this patent
Estimating the term…
Abstract
A plurality of multiplicand bit transmission lines and a plurality of multiplier bit transmission lines or their decoding signal transmission lines are arranged in a two-dimensional plane, and partial product generators are arranged at their intersections. A plurality of rows of first multi-input adders are arranged at predetermined numbers of rows, and at least one row of second multi-input adders are arranged at predetermined numbers of the first multi-input adders. A basic cell is formed by a predetermined number of partial product generators and one first multi-input adder, and the basic cells are repetitively arranged to obtain a rectangular configuration.
Claims18
An M.times.N-bit multiplier comprising:
- M multiplicand bit transmission lines arranged along a first direction;
- N multiplier bit transmission lines arranged along a second direction substantially perpendicular to the first direction;
- M.times.N partial product generators, each provided at one intersection between said multiplicand bit transmission lines and said multiplier bit transmission lines;
- R rows of M first multi-input adders comprising Wallace tree type adders arranged hierarchically and for adding output signals of S of said partial product generators located adjacently in a column, where R is at least two and less than N, and S=(N/R).gtoreq.5;
- and
- at least one row of M second multi-input adders comprising Wallace tree type adders arranged hierarchically and adding output signals of said first multi-input adders,
- said S partial product generators and one of said first multi-input adders forming one basic cell,
- M.times.R basic cells being repetitively arranged in a matrix corresponding to the arrangement of said first multi-input adders, each of said R basic cells in a column processing the same set of corresponding multiplicand bit signals, and the output signal lines of said basic cells being extended by predetermined bits along the second direction being connected to the corresponding said second multi-input adders arranged between the basic cell rows using repetitive line patterns forming a substantially rectangular layout configuration of said multiplier.
An M.times.N-bit multiplier having a layout configuration and comprising:
- M multiplicand bit transmission lines arranged along a first direction and transmitting multiplicand bit signals;
- N multiplier bit transmission lines arranged along a second direction substantially perpendicular to the first direction;
- M.times.N partial product generators, each provided at one intersection between said multiplicand bit transmission lines and said multiplier bit transmission lines;
- R rows of M first multi-input adders comprising wallace tree type adders arranged hierarchically and being arranged in an arrangement and adding output signals of S of said partial product generators located adjacently in a column, where R is at least two and less than N, and S=(N/R).gtoreq.5;
- and
- at least one row of M second multi-input adders comprising Wallace tree type adders arranged hierarchically and adding output signals of said first multi-input adders,
- wherein,
- said S partial product generators and one of said first multi-input adders forming one basic cell,
- M.times.R basic cells being repetitively arranged in a matrix corresponding to the arrangement of said first multi-input adders,
- each of R basic cells arranged in a column processing the same corresponding multiplicand bit signals,
- said basic cells having output signal lines extended by predetermined bits along the second direction to be connected to the corresponding said second multi-input adders arranged between the basic cell rows using repetitive line patterns forming a substantially rectangular layout configuration of said multiplier,
- each of said basic cells comprising four partial product generators and a four-input adder as one of the first multi-input adders, and
- output signal lines of said first multi-input adders are extended by predetermined bits in the second direction and are connected to said second multi-input adders in another column.
Dependencies are inferred from the claim text.