US 5,465,076 A · Programmable delay line programmable delay circuit and digital controlled oscillator

Abstract

A programmable delay line comprises a plurality of delay stages connected in series, each of the delay stages including: a basic path for passing an input signal; a delay path for passing the input signal with a predetermined delay time; and a selector for selecting either the basic path or the delay path to pass the input signal in accordance with digital data externally inputted, wherein differences in times for passing the input signal through the basic path and through the delay path in the plurality delay stages are UD.2.sup.n (n=0, 1, 2 . . . ), UD being unit delay time. A programmable delay apparatus comprises: an oscillator and counter, which determine a coarse delay time in accordance with the upper bit data of control data, and a programmable delay line, which determines a fine delay time according to the lower bit data of the control data after the finish of the coarse delay time to obtain a total delay time. The counter provides a wide range of available delay times. The oscillator of the programmable delay apparatus can be controlled by a control signal. Addition of a feedback circuit for supplying the delay signal from the delay line as the control signal to the oscillator of the programmable delay apparatus provides a digital controlled oscillator.

Claims17

Dependent claims

A programmable delay line comprising a plurality of delay stages connected in series, each of said delay stages including:

a basic path for passing an input signal;
a delay path for passing said input signal with a predetermined delay time;
and
a selector for selecting either of said basic path or said delay path to pass said input signal in accordance with digital data externally inputted, wherein a difference in the times for passing said input signal through said basic path and through said delay path in each of said plurality of delay stages is UD.2.sup.n (n=0, 1, 2, 3 . . . ), said UD being a possible minimum time difference between passing of said input signal through said basic path and through said delay path in each of said plurality of delay stages and said n being the number of the respective one of said delay stages, wherein at least said delay path comprises a delay means for providing said difference, wherein said delay means comprises one or more inverting circuits, and wherein said basic path in the last of said delay stages comprises three first inverting circuits having the same inverting interval and said delay path in the last of said delay stages comprises two of said first inverting circuits and a second inverting circuit having a delay time twice that of said first inverting circuit.

1 more element

A programmable delay apparatus comprising:

an oscillator responsive to an input signal for generating oscillation pulses at a predetermined interval;
means for counting said oscillation pulses and generating a detection signal delayed a first interval from said input signal when a count value of said counting means reaches a predetermined value;
a programmable delay line for delaying said detection signal for a second interval less than said predetermined interval to produce an output signal delayed by an amount corresponding to said first interval and said second interval from said input signal, said programmable delay line comprising a plurality of delay stages connected in series, each of said delay stages including:
a basic path for passing an input signal;
a delay path for passing said input signal with a predetermined delay time;
and
a selector for selecting either of said basic path or said delay path to pass said input signal in accordance with digital data externally inputted, wherein a difference in the times for passing said input signal through said basic path and through said delay path in each of said plurality of delay stages is UD.2.sup.n (n=0, 1, 2, 3 . . . ), said UD being a possible minimum time difference between passing of said input signal through said basic path and through said delay path in each of said plurality of delay stages and said n being the number of the respective one of said delay stages, wherein at least said delay path comprises a delay means for providing said difference, wherein said delay means comprises one or more inverting circuits, and wherein said basic path in the last of said delay stages comprises three first inverting circuits having the same inverting interval and said delay path in the last of said delay stages comprises two of said first inverting circuits and a second inverting circuit having a delay time twice that of said first inverting circuit;
and
control data supplying means, receiving digital control data having a predetermined number of bits indicative of a desired time for delaying said output signal from said input signal, for supplying upper bits of said digital control data to said counting means as said predetermined value, and for supplying lower bits of said digital control data to said programmable delay line as said digital data.

6 more elements

A programmable delay apparatus comprising:

an oscillator responsive to an input signal for generating oscillation pulses at a predetermined interval, wherein said oscillator comprises a ring oscillator having an odd number of inverting circuits connected in a ring and wherein one of said inverting circuits comprises a starting up circuit responsive to a control signal for starting oscillation of said ring oscillator;
means for counting said oscillation pulses and generating a detection signal delayed a first interval from said input signal when a count value of said counting means reaches a predetermined value;
a programmable delay line for delaying said detection signal for a second interval less than said predetermined interval to produce an output signal delayed by an amount corresponding to said first interval and said second interval from said input signal, said programmable delay line comprising a plurality of delay stages connected in series, each of said delay stages including:
a basic path for passing an input signal;
a delay path for passing said input signal with a predetermined delay time;
and
a selector for selecting either of said basic path or said delay path to pass said input signal in accordance with digital data externally inputted, wherein a difference in the times for passing said input signal through said basic path and through said delay path in each of said plurality of delay stages is UD.2.sup.n (n=0, 1, 2, 3 . . . ), said UD being a possible minimum time difference between passing of said input signal through said basic path and through said delay path in each of said plurality of delay stages and said n being the number of the respective one of said delay stages, wherein at least said delay path comprises a delay means for providing said difference, wherein said delay means comprises one or more .inverting circuits, and wherein said basic path in the last of said delay stages comprises three first inverting circuits having the same inverting interval and said delay path in the last of said delay stages comprises two of said first inverting circuits and a second inverting circuit having a delay time twice that of said first inverting circuit;
and
control data supplying means, receiving digital control data having a predetermined number of bits indicative of a desired time for delaying said output signal from said input signal, for supplying upper bits of said digital control data to said counting means as said predetermined value, and for supplying lower bits of said digital control data to said programmable delay line as said digital data.

6 more elements

Dependencies are inferred from the claim text.

Programmable delay line programmable delay circuit and digital controlled oscillator

Life of this patent

Programmable delay line programmable delay circuit and digital controlled oscillator

Life of this patent

Abstract

Claims17