Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein

A delay-locked-loop based clock synthesizer for generating, from a reference signal, a clock signal having a frequency different from a frequency of the reference signal, comprising:

• a frequency divider for generating a modified reference signal from said reference signal, wherein a frequency of said modified reference signal is equal to a frequency of said reference signal divided by a dynamically adjustable value;
• a delay-locked-loop circuit, comprising
• a controllable delay circuit, coupled to said frequency divider, comprising a plurality of controllable delay elements serially connected to one another, each of said delay elements delaying said modified reference signal by an adjustable quantum of time such that said delay elements generate a plurality of delayed signals offset in time from one another and from said modified reference signal,
• a first multiplexer, coupled to two or more of said delay elements, for receiving the delayed signals generated by said two or more of said delay elements, and for routing one of said received delayed signals to an output of said first multiplexer,
• a phase detector, connected to said output of said first multiplexer, for receiving said routed delayed signal and said modified reference signal, and for generating a control signal indicative of a difference between a phase of said routed delayed signal and a phase of said modified reference signal, and
• feedback means, connected to said delay elements and said phase detector, for transferring said control signal from said phase detector to said delay elements, wherein each of said delay elements adjusts, in accordance with said control signal, said quantum of time by which they each delay said modified reference signal, such that said phase of said modified reference signal is synchronized with said phase of said routed delayed signal;
• one or more mixing circuits, each of said mixing circuits connected to said controllable delay circuit and associated with one of said two or more delay elements, said mixing circuits comprising combinational networks for logically combining said delayed signals such that said mixing circuits generate logically combined signals;
• and
• a second multiplexer, connected to said mixing circuits, for receiving said logically combined signals and for routing one of said logically combined signals to an output of said second multiplexer, wherein said routed logically combined signal represents said clock signal.