Sorting processor

Abstract

A sorting processor has a polygonal priority order generating circuit. The polygonal priority order generating circuit includes a memory for storing information of centers of plural polygons; a position setting section for transforming a coordinate of each of the polygonal centers from an object coordinate to an absolute coordinate; and a visual field transforming circuit for transforming the transformed coordinate as a position set object obtained by the position setting section with respect to a visual field. The sorting processor further has a sorting circuit for sorting transformed results about the visual field on the basis of Z-axis information. There is no frame delay due to a need to wait until the polygonal information is completely sorted. Further, it is not necessary to use a RAM for storing information geometrically transformed before a sorter.

Dependencies are inferred from the claim text.