Test access port controlled built in current monitor for IC devices

An integrated circuit device having CMOS circuit modules coupled between high and low potential power rails, at least one built-in current (BIC) monitor coupled between a CMOS circuit module and low potential power rail for monitoring the level of static or quiescent current (IDDQ) said BIC monitor being constructed to provide a digital code fault signal at an output according to the monitored level of static current (IDDQ), and a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin and a TAP data output (TDO) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register (BSR/TDR1) for applying test vectors at data inputs of the IC device for performing boundary scan testing, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control and clock signals and to direct control and clock signals controlling operation of the TIR and TDR's, comprising:

• a MOS bypass transistor having a primary current path coupled in parallel with the BIC monitor between the CMOS circuit module and low potential power rail;
• said TDR's comprising a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin, said BICSC TDR having an output coupled to a control node of the MOS bypass transistor for controlling a conducting state of the MOS bypass transistor according to the coded BIC monitor bypass code (BICBC);
• said MOS bypass transistor providing a low impedance bypass path around the BIC monitor in response to a first BICBC during normal operation of the IC device, said MOS bypass transistor presenting a high impedance bypass path in response to a second BICBC for monitoring the level of static current (IDDQ) at the BIC monitor;
• said TDR's also comprising a design specific BIC fault capture TDR (BICFCP TDR) coupled to an output of the BIC monitor for receiving and storing digitally coded fault signals according to the monitored level of static current (IDDQ) and for shifting out fault signals to the TDO pin.

A method of monitoring the level of static current (IDDQ) from a MOS or CMOS circuit module coupled between high and low potential power rails of an integrated circuit (IC) device, said IC device having a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin and a TAP data output (TDO) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register (BSR/TDR1) for applying test vectors at the inputs of the IC device for performing boundary scan testing, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control and clock signals and to direct control and clock signals controlling operation of the TIR and TDR's, said IC device also having a built-in current (BIC) monitor coupled between the MOS or CMOS circuit module and low potential power rail, said method comprising:

• bypassing each BIC monitor using a bypass or shunt circuit coupled in parallel with the BIC monitor between the CMOS circuit module and low potential power rail;
• controlling the conducting state of the bypass or shunt circuit using a design specific BIC shunt control TDR (BICSC TDR) of the test access port (TAP) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin and coupled to the bypass or shunt circuit for controlling the conducting state of the bypass or shunt circuit according to the coded BIC monitor bypass code (BICBC);
• providing a low impedance bypass path around the BIC monitor through the bypass or shunt circuit in response to a first BICBC during normal operation of the IC device;
• presenting a high impedance bypass path through the bypass or shunt circuit in response to a second BICBC for monitoring the level of static current (IDDQ) at the BIC monitor during a test mode operation.

An integrated circuit device comprising:

• a MOS or CMOS circuit module coupled between high and low potential power rails;
• a built in current (BIC) monitor coupled between the MOS or CMOS circuit module and low potential power rail for monitoring the level of static or quiescent current (IDDQ), said BIC monitor being constructed to provide a digital code fault signal at an output according to the monitored level of static or quiescent current (IDDQ);
• a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin and a TAP data output (TDO) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register (BSR/TDR1) for applying test vectors at data inputs of the IC device for performing boundary scan testing, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control and clock signals and to direct control and clock signals controlling operation of the TIR and selected TDR's;
• a bypass or shunt circuit coupled in parallel with the BIC monitor between the MOS or CMOS circuit module and low potential power rail said bypass or shunt circuit having a low impedance conducting state and a high impedance conducting state and control means for controlling the conducting state of the bypass or shunt circuit;
• said TDR's comprising a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin, said BICSC TDR having an output coupled to the control means for controlling the conducting state of the bypass or shunt circuit according to the coded BIC monitor bypass code (BICBC);
• said bypass or shunt circuit providing a low impedance bypass path around the BIC monitor in response to a first BICBC during normal operation of the IC device, said bypass circuit presenting a high impedance bypass path in response to a second BICBC for monitoring the level of static or quiescent current (IDDQ) at the BIC monitor.