Real-time DC offset control and associated method

A method of cancelling DC offset while receiving an analog signal having a periodic sinusoidal portion comprising the steps of:

• (a) quantizing the received signal into digital sample values at discrete time intervals;
• (b) generating a DC offset error value by adding sample values taken one-half period apart during reception of the sinusoidal preamble portion;
• (c) obtaining a scaled correction value by multiplying each of said plurality of DC offset error values by a loop gain factor divided by two;
• (d) inputting said scaled correction value into an accumulator for accumulating a DC offset correction value;
• (e) outputting a DC offset correction value from said accumulator;
• (f) converting said DC offset correction value into an analog offset adjustment signal;
• (g) subtracting said analog offset adjustment signal from the received analog signal;
• (h) repeating the steps of quantizing the received signal through subtracting said analog offset adjustment signal until a stabilized DC offset correction value has been obtained;
• (i) holding said stabilized DC offset correction value at the output of said accumulator;
• (j) repeatedly converting said DC offset correction value into an analog offset adjustment signal;
• and
• (k) subtracting said stabilized DC offset correction value from said received analog signal during reception of the rest of the signal.

A DC offset control loop comprising:

• a summing junction having a first input and a second input and an output, said first input connected to analog signal processing elements;
• an analog to digital converter, having an input and an output, said analog to digital converter input connected to said output of said summing junction;
• a first memory circuit having a first memory input connected to said output of said analog to digital converter and a first memory output;
• a second memory having a second memory input connected to the first memory output and a second memory output,
• a first adder circuit having an input and an output, said first adder input connected to said second memory output and to said first memory input;
• a multiplier circuit having a multiplicand input connected to said output of said first adder circuit, a multiplier input connected to a source of a predetermined multiplier value, and an output;
• an accumulator circuit having an input connected to said output of said multiplier circuit and an output;
• and
• a digital to analog converter having an input connected to said output of said integrator circuit and an output connected to said second input of said summing junction.

In a disk storage drive a DC offset control loop comprising:

• subtraction means for subtracting a DC offset adjustment signal from an analog input signal read from a recording surface of a magnetic recording disk, said input signal including a constant frequency preamble burst portion having a known period and a data portion, said subtraction means outputting a difference signal obtained from said subtraction;
• sampling means connected to said subtraction means for sampling and quantizing said difference signal into digital sample values;
• adder means for receiving said digital sample values and adding digital sample values which are opposite in sign as sampled to obtain a series of DC offset error values;
• multiplier means for scaling said DC offset error values by a loop gain factor;
• and
• integrator means connected to said multiplier means for accumulating said scaled DC offset error values and outputting an DC offset correction value to a digital to analog converter, said digital to analog converter receiving said output from said integrator means and generating said DC offset adjustment signal input to said subtraction means.

In a disk storage drive a DC offset control loop comprising:

• a summing junction having a first input, a second input and an output, the first input being connected to analog signal processing elements of a read channel within the disk storage drive,
• an analog to digital converter, having an input connected to said sampling circuit for sampling a known frequency portion of an analog signal read back from a data storage disk and received from said summing junction for determining a series of intermediate DC offset correction values;
• a first memory circuit having a first memory input connected to said output of said analog to digital converter and having a first memory output;
• a second memory circuit having an input connected to the first memory output and having a second memory output;
• an adder circuit having an adder input and an adder output for providing a series of DC offset error values, said adder input being connected to said second memory output and said first memory input;
• a digital to analog converter having an input connected to said adder output, and having an output connected to a feedback signal path extending to said second input of said summing junction, for converting said series of DC offset error values into an analog control signal;
• and,
• an integrator circuit connected in said feedback signal path for integrating over a first predetermined time interval the analog control signal put out by said digital to analog converter, for holding the integrated analog control signal during a second predetermined time interval and for supplying an integrated DC offset error value to the second input of the summing junction during at least the second predetermined time interval.