Process for fabricating a semiconductor device using dual planarization layers

A process for fabricating a semiconductor device comprising the steps of:

• providing a substrate having elevated and recessed regions therein;
• oxidizing the recessed regions to form a dielectric liner overlying the recessed regions;
• forming a fill material overlying the elevated regions and filling the recessed regions;
• removing a portion of the fill material overlying the elevated regions;
• forming an etch stop layer overlying the elevated regions and the fill material;
• and
• removing portions of the etch stop layer and the fill material to form a planar surface.

A process for fabricating a semiconductor device comprising the steps of:

• providing a substrate having a first planarization layer overlying the substrate, the first planarization layer having an opening therein exposing a portion of the substrate;
• etching the substrate to form a trench in the exposed portion of the substrate;
• oxidizing the substrate to form a dielectric liner overlying the trench;
• depositing a fill material to overlie the first planarization layer and to fill the trench;
• etching the fill material to expose portions of the first planarization layer;
• depositing a second planarization layer to overlie the fill material and the exposed portions of the first planarization layer;
• and
• polishing back the second planarization layer and the fill material to form a planar surface.