US 5,457,400 AGranted

Semiconductor array having built-in test circuit for wafer level testing

AssigneeMicron Technology, Inc.

InventorsAftab Ahmad, Larren G. Weber, Robert S. Green

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Abstract

A test circuit is provided for an integrated circuit device, whereby an oscillator is provided on-chip and is activated by a test circuit. The test circuit provides an ability to test the devices while still on the wafer and facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. The oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the DUT at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.

Claims18

Dependent claims

In an integrated circuit device formed on a semiconductor wafer and having functional circuitry, a test circuit for testing the functional circuitry, said test circuit comprising:

a) an oscillator circuit formed on said integrated circuit device for providing a periodic output;
b) the oscillator circuit including circuitry for varying a period of the periodic output in order to vary a test parameter;
c) circuitry for receiving the periodic output from the oscillator circuit and providing a timing signal to the functional circuitry of the integrated circuit device as a device under test DUT, the timing signal having a period which is proportional to the periodic output, said timing signal controlling test sequences during said testing of the functional circuitry, such that a variation in the test parameter as a result of varying the period of the periodic output permits the response of the functional circuitry of the DUT at different operating speeds to be determined;
d) a scanning circuit for determining outputs of the functional circuitry;
and
e) a response circuit responsive to the scanning circuitry for providing an error signal during said testing;
and
f) a nonvolatile memory responsive to the error signal for retaining an indication of test results.

5 more elements

In an integrated circuit device formed on a semiconductor wafer and having a functional circuit array, a test circuit for testing the functional circuit array, said test circuit comprising:

a) a burnin circuit formed on the integrated circuit device, in electrical communication with the functional circuit array and which permits the functional circuit array to be selectively operated in a normal operating mode by which the functional circuit array may be addressed through external connections and a burnin code, and in which the burnin circuit causes the integrated circuit device to cycle through predetermined sequences for addressing at least a substantial portion of the functional circuit array;
b) an oscillator circuit formed on the integrated circuit device in electrical communication with the burnin circuit for providing a periodic output;
c) the oscillator circuit including circuitry for varying the period of the periodic output of the oscillator circuit;
d) circuitry in electrical communication with the oscillator circuit for receiving the periodic output from the oscillator circuit and providing a timing signal to the functional circuit array, the timing signal having a period which is proportional to the periodic output, such that a variation in a test parameter with a variation in the period of the periodic output permits the response of the functional circuit array at different operating speeds to be determined;
e) scanning circuitry for determining outputs of the functional circuit array;
f) a response circuit responsive to the scanning circuitry for providing an error signal;
and
g) a nonvolatile memory responsive to said error signal for retaining an indication of test results.

5 more elements

Dependencies are inferred from the claim text.