Apparatus and method for stacking integrated circuit devices
AssigneeNCR Corporation
InventorDonald F. Nickel
Life of this patent
Estimating the term…
Abstract
An apparatus and method for stacking integrated circuit devices which combine flip-chip technology and soldering methods with laminated stack frames to provide a vertical stack array with minimal parasitic inductance. Each laminated stack frame has a central cavity and includes a plurality of vias extending through them. The vias have top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump. Each laminated stack frame also includes a plurality of solder bump pads extending into the cavity to contact corresponding solder bumps on a flip-chip integrated circuit chip, and a plurality of traces coupling each solder bump pad to a via. The bottom surfaces of the vias of a bottom laminated stack frame couple to contacts on a printed circuit board.
Claims13
An apparatus for mounting a flip-chip integrated circuit chip to a printed circuit board comprising:
- a laminated stack frame having a central cavity and including a plurality of vias extending through the laminated stack frame, wherein the vias have top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump which is coupled to a contact on the printed circuit board, the laminated stack frame also including a plurality of solder bump pads extending into the cavity to contact corresponding solder bumps on the flip-chip integrated circuit chip, and a plurality of traces coupling each of the solder bump pads to a corresponding via.
An apparatus for mounting a flip-chip integrated circuit chip to a printed circuit board comprising:
- a first laminated stack frame having a central cavity and including a plurality of vias extending through the first laminated stack frame, wherein the vias of the first laminated stack frame have top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump, the first laminated stack frame also including a plurality of solder bump pads extending into the cavity to contact corresponding solder bumps on a first flip-chip integrated circuit chip, and a plurality of traces coupling each of the solder bump pads to a corresponding via;
- and
- a second laminated stack frame below the first laminated stack frame having a central cavity and including a plurality of vias extending through the second laminated stack frame, wherein the vias of the second laminated stack frame have top surfaces and bottom surfaces, wherein the top surfaces contact the bottom surfaces of the vias of the first laminated stack frame and wherein the bottom surfaces each contain a solder bump which couples to a contact on the printed circuit board, the second laminated stack frame also including a plurality of solder bump pads extending into the cavity to contact corresponding solder bumps on a second flip-chip integrated circuit chip, and a plurality of traces coupling each of the solder bump pads to a corresponding via.
A method for mounting a plurality of flip-chip integrated circuit chips to a printed circuit board comprising the steps of:
- providing a first laminated stack frame including a central cavity and a plurality of vias extending through the first laminated stack frame and having top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump;
- coupling a trace extending into the cavity to each of the vias;
- coupling a solder bump pad to each of the traces;
- coupling a plurality of solder bumps on a first flip-chip integrated circuit chip to the solder bump pads;
- providing a second laminated stack frame having a central cavity and including a plurality of vias extending through the second laminated stack frame and having top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump;
- coupling a trace extending into the cavity of the second laminated stack frame to each of the vias of the second laminated stack frame;
- coupling a solder bump pad to each of the traces of the second laminated stack frame;
- coupling a plurality of solder bumps on a second flip-chip integrated circuit chip to the solder bump pads of the second laminated stack frame;
- vertically stacking the first laminated stack frame on top of the second laminated stack frame to form a vertical stack array such that the bottom surfaces of each of the vias of the first laminated stack array contact the top surfaces of each of the vias of the second laminated stack frame below;
- and
- coupling the vertical stack array on top of the printed circuit board such that the bottom surfaces of the vias of the second laminated stack frame couple to contacts on the printed circuit board.
Dependencies are inferred from the claim text.