High density data compression encode/decode circuit apparatus and method of using in local area networks

A data processing system apparatus, said apparatus comprising:

• an encode circuit member for encoding binary data in a pulse position modulation (PPM) format;
• a plurality of delay elements associated with said encode circuit member;
• and
• a delay calibration circuit associated with said encode circuit member for calibrating said plurality of delay elements to encode said binary data in an enhanced PPM encoded format, said delay calibration circuit comprising a phase-lock loop (PLL) and precision crystal oscillator circuit combination that provides a reference delay for calibrating said delay elements,
• said enhanced PPM encoded format comprises binary data bits encoded such that each occurrence of a first binary state comprises a first time period and each occurrence of a second binary state comprises a second slightly greater time period, said first and second time periods being controlled by said delay calibration circuit, said second slightly greater time period being in the range of 10% to 30% greater than said first time period and said first and second time periods being measured in nanoseconds.

A data compression circuit apparatus, said apparatus comprising:

• an encode circuit member for encoding binary data in a pulse position modulation (PPM) format;
• a plurality of delay elements associated with said encode circuit member;
• and
• a delay calibration circuit, said delay calibration circuit comprising a phase-lock loop (PLL) and precision crystal oscillator circuit combination that provides a reference delay for calibration said plurality of delay elements to facilitate encoding said binary data in an enhanced PPM encoded format, said enhanced PPM encoded format comprises binary data bits being encoded such that each occurrence of a first binary state comprises a first time period and each occurrence of a second binary state comprises a second slightly greater time period.

A data compression circuit apparatus, said apparatus comprising:

• an encode circuit member for encoding binary data in a pulse position modulation (PPM) format;
• a plurality of delay elements associated with said encode circuit member;
• and
• a delay calibration circuit, said delay calibration circuit comprising a phase-lock loop (PLL) and precision crystal oscillator circuit combination that provides a reference delay for calibrating said plurality of delay elements to facilitate encoding said binary data in an enhanced PPM encoded format, said delay calibration circuit facilitates 98% data throughput, and said enhanced PPM encoded format comprises binary data bits encoded such that each occurrence of a first binary state comprises a first time period and each occurrence of a second binary state comprises a second slightly greater time period, said first and second time periods being controlled by said delay calibration circuit, said second slightly greater time period being in the range of 10% to 30% greater than said first time period and said first and second time periods being measured in nanoseconds.

A method of reducing data recovery amplitude resolution factor in encoded data signals, said method comprising the steps of:

• (a) providing a delay element calibration circuit for use in an encoder to facilitate encoding data in an enhanced PPM encoded format;
• (b) encoding data in PPM signal format such that each occurrence of a first data state comprises a first time period and each occurrence of a second data state comprises a second slightly greater time period than said first time period, said first and second time periods being controlled by said delay element calibration circuit, said second slightly greater time period being in the range of 10% to 30% greater than said first time period;
• and
• (c) decoding said encoded PPM data signal, said decoded signal having an amplitude resolution factor of less than 60%.

A decoding circuit apparatus, said apparatus comprising:

• a decode circuit member for decoding binary data previously encoded in pulse position modulation (PPM) encoded format;
• a plurality of delay elements associated with said decode circuit member;
• and
• a delay calibration circuit, said delay calibration circuit comprising a phase-lock loop (PLL) and precision crystal oscillator circuit combination that provides a reference delay for calibrating said plurality of delay elements to facilitate delaying said previously encoded binary data by a time period that assures placement of an encoded data bit into its proper decode value.