US 5,450,557 A · Single-chip self-configurable parallel processor

Abstract

A self-contained, self-configurable cascadable pipelined processor chip (160) is diclosed. The chip contains a computation section (FIGS. 1a-1d) which consists of various types of computation circuits (20-42) that can be software-interconnected in any desired configuration by a set of multiplexers (44-52) whose settings are under the control of a control section (FIG. 2 ). The control section consists of various types of control circuits (60-76) which are also software-interconnectable in any desired configuration under program control. The chip (160) is configured by a very long instruction word and then executes the algorithm defined by that configuration iteratively until stopped. The chip (160) can be programmed to reconfigure itself in response to computation results or other selectable parameters, either in accordance with internally stored configurations or in accordance with configuration information stored in an external random access memory (56, 58). Internal reconfiguration requires no separate reconfiguration time at all, and external reconfiguration can be accomplished in less than 10 .mu.s.

Claims9

Dependent claims

A configurable programmable processor, comprising:

a) a circuit chip;
b) computational circuit means on said chip for performing computations;
c) a plurality of first multiplexer means on said chip for selectively connecting said computational circuit means to iteratively calculate selectable algorithms, each of said first multiplexer means having at least one input and at least one output;
d) a plurality of second multiplexer means on said chip for controlling the interconnections of said first multiplexer means;
e) means enabling any output of any of said first multiplexer means to be selectably directly unidirectionally interconnected with any input of any of said first multiplexer means by said second multiplexer means;
f) latch register means on said chip for supplying, during iterative computations, a plurality of selectable control values to each of said second multiplexer means, said latch register means including means causing said latch register means to be programmable from outside of said chip;
and
g) control means on said chip for controlling the selection of said control values by said second multiplexer means independently of any control input from outside said chip.

5 more elements

Dependencies are inferred from the claim text.

Single-chip self-configurable parallel processor

Life of this patent

Single-chip self-configurable parallel processor

Life of this patent

Abstract

Claims9