System direct memory access (DMA) support logic for PCI based computer system

An information processing system, comprising:

• a central processing unit (CPU);
• a first system bus which connects said CPU to system memory so that said CPU can read data from, and write data to, said system memory;
• a second system bus connected to said CPU;
• a host bridge connecting said second system bus to a peripheral bus having at least one peripheral device, including an active input/output (I/O) bridge, attached thereto;
• said active I/O bridge connecting said peripheral bus to a standard I/O bus, said standard I/O bus having a plurality of standard I/O devices attached thereto;
• arbitration logic located within said active I/O bridge which functions in an arbitration mode for arbitrating between said plurality of standard I/O devices competing for access to said standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to said standard I/O bus;
• a direct memory access (DMA) controller for performing DMA cycles over said peripheral bus for said selected standard I/O device wherein data is transferred between said system memory and said selected I/O device without intervention by said CPU;
• and
• direct memory access (DMA) support logic residing on said second system bus for enabling said DMA cycles to be performed over said peripheral bus, wherein said DMA support logic includes sideband signals directly connecting said DMA support logic to said active I/O bridge independently of said host bridge, said sideband signals including (i) a DMA active line which is driven high by said DMA controller and read by said active I/O bridge to determine if said DMA controller is active, and (ii) a transfer complete line which is driven high by said DMA controller add read by said active I/O bridge to determine if data transfer into or out of said active I/O bridge has been completed.