Content addressable memory implementation with random access memory
AssigneeInternational Business Machines Corporation
InventorMattheus C. A. Heddes
Life of this patent
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Abstract
A content addressable memory (CAM) implementation using random access memory (RAM) and a method for operating the implementation are described, wherein the RAM is divided into smaller, individually addressable units, which are addressed by a subword of the applied keyword, and the outputs of which are bitwise ANDed. The result of the bitwise AND operation is used to activate the matching lines of the CAM implementation. The new implementation allows the use of conventional circuit design.
Claims9
A content addressable memory (CAM) implementation for a W bit wide keyword, applied to a set of input lines, and a set of N possible matching lines with a random access memory (RAM) addressable by said keyword, wherein said RAM consists of m individually addressable memory units each having an N-bit wide output, address lines of each of said m memory units are connected to a subset of the input lines for the keyword, and the outputs of said m memory units are connected to a gate performing a bitwise AND operation, the output of which serves to activate a subset of said N possible matching lines.
A method for operating a content addressable memory (CAM) implementation for a W-bit wide keyword and a set of N possible matching lines, said implementation comprising of m individually addressable memory units and a gate bitwise ANDing the data outputs of said m memory units, wherein the m memory units are loaded with a 1 at a position determined by the matching line assigned to the addressing keyword;
- the keyword is divided into m subwords, each subword is used to address each of said m memory units, and the data outputs of said m memory units are bitwise ANDed resulting in an N-bit output word used to activate a matching line assigned to the keyword applied.
Dependencies are inferred from the claim text.