Boundary scan architecture extension
AssigneeBull HN Information Systems Inc.
InventorRobert J. Russell
Life of this patent
Estimating the term…
Abstract
A method and apparatus provides improved modes of operation of a standard test bus based on a standard boundary scan architecture which minimizes the number of bits required to be serially scanned into the controllers of the various devices connected to the bus by temporarily disabling scan paths not required to be utilized. Means for continuously verifying the inoperative state of test logic and for diagnosing test logic faults are also described.
Claims20
A test access port (TAP) included in an integrated circuit (IC) device for testing circuits within said device, said TAP having a standard interface which consists of a number of lines including a test data output (TDO) and a test data input (TDI) for use in testing and a controller for generating control and clocking signals for carrying out said testing, said TAP further comprising a plurality of standard registers connected to said controller and a multiplexer having a number of inputs and an output connected to said TDO line of said IC device, each register having at least a serial input and a serial output, said serial input of each register being connected to said TDI of said standard interface and said serial output of each register being connected to a different one of said multiplexer inputs, said TAP further including:
- an additional number of register like transfer circuits, each register like transfer circuit having an input and an output, said input of each of said number of register like transfer circuits being connected to said TDI line and said output of each transfer circuit being connected to a different predetermined one of said inputs of said multiplexer;
- and,
- an instruction register for storing information pertaining to any one of a number of instructions coded for generating signals defining a number of operational modes, said instruction register being coupled to said multiplexer and to said controller, said instruction register in response to a first one of said number of instructions being applied by said TDI line causing said multiplexer to select and during said testing, maintain selected as a path between said TDI and TDO lines of said IC device, a first one of said number of said register like transfer circuits to effectively provide a minimum length shift path for minimizing the number of bits required to be shifted through a string of IC devices for carrying out said testing.
A method of providing a number of additional modes of operation in a standard test access port (TAP) for minimizing shifting of instruction and data bits through a number of series connected integrated circuit (IC) devices, said standard TAP being included in each integrated device for testing circuits within said device, said TAP having a standard interface which consists of a number of lines including a test data output (TDO) line and a test data input (TDI) line for use in testing and a controller for generating control and clocking signals for carrying out said testing, said TAP further comprising a plurality of standard registers connected to said controller and a multiplexer having a number of inputs and an output connected to said TDO line of said IC device, each register having at least a serial input and a serial output, said serial input of each standard register being connected to said TDI line of said standard interface and said serial output of each register being connected to a different one of said multiplexer inputs, said method comprising the steps of:
- a. incorporating an additional number of register like transfer circuits into each IC device, each register like transfer circuit having an input and an output;
- b. connecting said input of each register like transfer circuit to said TDI line and connecting said output of each register like transfer circuit to a different predetermined input of said multiplexer;
- c. including an instruction register for storing information pertaining to any one of a number of instructions coded for generating signals defining said number of additional modes;
- d. connecting said instruction register to said TDI line, to said multiplexer and to said controller;
- e. selecting in response to a first one of said number of instructions being loaded into said register through said TDI line, one of said additional number of register like transfer circuits designated by said instruction as a path between said TDI and TDO lines of said IC device;
- and,
- f. maintaining the selection of said one register like transfer circuits during testing so as to provide a minimum length shift path for minimizing said shifting of said data and instruction bits.
Dependencies are inferred from the claim text.