Method for manufacturing a semiconductor memory device having a capacitor with increased effective area

A method for manufacturing a capacitor of a semiconductor device, comprising the steps of:

• (a) sequentially forming an end-of-etch detection layer on a semiconductor substrate and a second spacer layer on said end-of-etch layer;
• (b) forming a first conductive layer with an upper surface having a plurality of topographical valleys thereon on said second spacer layer;
• (c) forming a first material layer on said first conductive layer;
• (d) forming a photoresist pattern on said first material layer for defining individual cell units;
• (e) anisotropically etching said first material layer and first conductive layer using said photoresist pattern to form a first etched material pattern and a first etched conductive pattern;
• (f) isotopically etching said first etched material pattern, thereby forming a second material etched pattern which is smaller than said first etched material pattern;
• (g) removing said photoresist pattern;
• (h) partially etching an upper edge portion of said first etched conductive pattern using said second etched material pattern as an etching mask, thereby forming a second etched conductive pattern having a hummock adjacent an upper peripheral edge thereof;
• (i) removing second etched material pattern and a portion of said second spacer layer;
• (j) forming a mask layer on the surface of the resultant structure after step (i);
• (k) etching back said mask layer by detecting an end-point of etching using said end-of-etch detection layer to form an etching mask deposited in said valleys and a spacer formed on said hummock;
• and
• (l) anisotropically and partially etching said second etched conductive pattern using said etching mask and said spacer, thereby forming a main electrode of capacitor having a plurality of microtrenches and micropillars therein.

A method for manufacturing a capacitor of a semiconductor device comprising the steps of:

• (a) sequentially forming a first conductive layer on a semiconductor substrate and forming a first material layer on said first conductive layer;
• (b) patterning said first material layer to form a first material pattern for defining said first conductive layer into individual cell units;
• (c) partially etching said first conductive layer using first material pattern as an etching mask, to thereby form a first conductive pattern having grooves between adjacent individual cell units, said grooves defining sidewall portions of said cell units;
• (d) forming spacers on said sidewall portions;
• and
• (e) etching said first conductive pattern using said spacers and said first material pattern as an etching mask to form a first conductive pattern having a hummock on an upper edge therearound.

A method for manufacturing a semiconductor device comprising the steps of:

• (a) sequentially stacking a first spacer layer, an end-of-etch detection layer, a second spacer layer, a first conductive layer, and a first material layer on a semiconductor substrate, said first conductive layer having an uneven upper surface having a plurality of valleys;
• (b) patterning said first material layer to form a first material mask pattern for defining individual cell units;
• (c) partially etching said first conductive layer using said first material mask pattern as an etching mask, thereby forming a first conductive pattern having grooves between adjacent individual cell units;
• (d) forming spacers on sidewalls of said cell units;
• (e) etching said first conductive pattern using said spacers and said first material mask pattern as an etching mask to form an etched first conductive pattern defined into individual cell units, each unit having a hummock formed on an upper edge therearound
• (f) forming a granular polysilicon layer covering the resultant structure obtained after forming said etched first conductive pattern;
• (g) etching back said granular polysilicon layer to leave a granular polysilicon pattern on a peripheral sidewall of each said cell unit of said first conductive pattern;
• (h) removing said spacers and said first material pattern;
• (i) depositing a mask material layer on the surface of the resultant structure after step (h);
• (j) etching back said mask material layer to form an etching mask in said valleys of said conductive pattern;
• and
• (k) partially etching said first conductive pattern using said etching mask of step (j) to form a main electrode of a capacitor having microtrenches and micropillars.