Equalizer for data receiver apparatus
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsMitsuru Uesugi, Kazuhisa Tsubaki, Kouichi Honma
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Abstract
In an equalizer including a plurality of delay elements, a plurality of weighting elements and an adder, the impulse response of a signal transmission channel is estimated to selectively switch over a plurality of selector switches associated with the inputs and outputs of the respective delay elements, thereby selectively changing the combination of the delay elements and the weighting elements transmitting an input signal from the channel to the adder and also changing the combination of the adder and a delay element feeding back the output of the discriminator to the adder. Thus, the number of required taps of the equalizer can be reduced, so that the power consumption and size of the equalizer can be reduced.
Claims2
A data receiver apparatus including:
- a memory storing a received signal transmitted through a signal transmission channel and demodulated into its baseband signal by a demodulator;
- an equalizer equalizing the received signal to provide an equalized output signal;
- an error corrector correcting any error included in the output signal from said equalizer to provide an error corrected output signal;
- and
- a voice decoder decoding voice data of the output signal of said error corrector,
- said equalizer comprising:
- a plurality of delay elements successively delaying the received signal applied to said equalizer from said memory to provide successively delayed output signals;
- a plurality of weighting elements multiplying the received signal from said memory and the successively delayed output signals from said plurality of delay elements by their weight coefficients respectively;
- an adder adding output signals from said weighting elements to obtain a result of addition;
- a discriminator converting the result of addition by said adder into a predetermined amplitude;
- feedback paths including a further delay element for feeding an output of said discriminator back to the respective output terminals of said plurality of delay elements;
- a plurality of selector switches;
- and
- control means for selecting said feedback paths to selectively connect output terminals of said plurality of delay elements to the input terminals of said plurality of weighting elements.
Dependencies are inferred from the claim text.