Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals

A synchronous semiconductor memory device comprising:

• a) a memory cell array implemented by a plurality of addressable memory cells;
• b) an input and output unit for supplying data bits from and to said memory cell array;
• c) an addressing system responsive to external address signals for selectively coupling said input and output unit with said plurality of addressable memory cells;
• d) a timing generator responsive to external command signals for controlling said input and output unit and said addressing system;
• and
• e) an input circuit responsive to an external clock signal and an external clock enable signal for producing a main internal control signal, said main internal control signal causing said timing generator to latch said external command signals, said input circuit having
• e-1) a first input stage assigned to said external clock signal, and enabled with an enable signal, said first input stage being operative to produce an internal clock signal synchronous with said external clock signal,
• e-2) a second input stage assigned to said external clock enable signal, and enabled with said enable signal, said second input stage being operative to produce an internal clock enable signal synchronous with said external clock enable signal,
• e-3) a first controller responsive to said internal clock signal for producing a first internal control signal maintained at a first level for a predetermined time period, and
• e-4) a second controller responsive to said first internal control signal for introducing a time delay between said internal clock enable signal and a second internal control signal, said second internal control signal allowing said first controller to produce said main internal control signal from said internal clock signal maintained at the first level for said predetermined time period.