Duty discriminating circuit

A duty ratio discriminating circuit for discriminating a ratio of a high-level precedent portion to one period of an information signal whose level varies periodically, on the basis of threshold values, which comprises:

• a sequencer for outputting a shift signal to obtain a first threshold level, by detecting the precedent portion of the information signal to output a sampling signal, detecting a subsequent portion of the information signal to output a latch signal, and detecting both the precedent and subsequent portions of the information signal to output a reset signal,
• a counter circuit reset in response to the reset signal, for counting reference clock signals;
• a latch circuit for latching count data counted as a precedent portion time period data by said counter circuit in response to the latch signal;
• a shift circuit for shifting the count data latched by said latch circuit by (2-n) times (where n denotes zero or a natural number) in bit unit on the basis of the shift signal outputted by said sequencer, and for outputting the shifted counted data;
• a comparator circuit for comparing the count data outputted by said counter circuit with a second threshold value corresponding to the shifted count data outputted by said shift circuit and for outputting a comparison result signal when the count data is larger than the shifted count data;
• and
• an output circuit for outputting the comparison result signal as a discriminate result signal on the basis of a level of the information signal and the sampling signal.

A duty ratio discriminating circuit for discriminating a ratio of a high-level precedent portion to one period of an information signal whose level varies periodically, on the basis of a threshold value, which comprises:

• a sequencer for outputting a sampling signal by detecting the precedent portion of the information signal, for outputting a latch signal by detecting a subsequent portion of the information signal, and for outputting a reset signal by detecting both the precedent and subsequent portions of the information signal;
• a counter circuit reset in response to the reset signal, for counting reference clock signals to obtain count data;
• a latch circuit for latching the count data counted by said counter circuit as a precedent portion time period data in response to the latch signal to obtain a latch data;
• a comparator circuit for comparing the count data outputted by said counter circuit with the latch data outputted by said latch circuit and for outputting a comparison result signal when the count data is larger than the latch data;
• and
• an output circuit for outputting the comparison result signal as a discriminate result signal on the basis of a level of the information signal and the sampling signal.