CMOS latchup suppression by localized minority carrier lifetime reduction

A method of manufacturing a CMOS integrated circuit with latchup suppression, said method comprising the steps of:

• defining a subsurface region of a silicon substrate, wherein the subsurface region is located beneath and is generally parallel to an upper surface of the silicon substrate;
• implanting minority carrier lifetime reducing impurities through a plurality of pairs of regions within the upper surface of the silicon substrate and into the subsurface region of the silicon substrate, wherein within each one of the plurality of pairs of upper surface regions the impurities beneath one upper surface region are not in contact with the impurities beneath the other upper surface region, and wherein the impurities are selected from the group consisting of calcium and strontium;
• and
• forming a plurality of transistors within the silicon substrate, wherein each transistor includes a source region and a drain region, and wherein the source and drain regions for each transistor together comprise one pair of the plurality of pairs of upper surface regions.

A method of manufacturing a CMOS integrated circuit with latchup suppression, said method comprising the steps of:

• defining a plurality of subsurface regions of a silicon substrate, wherein each subsurface region is located beneath and is generally parallel to an upper surface of the silicon substrate;
• implanting minority carrier lifetime reducing impurities into the plurality of subsurface regions of the silicon substrate, wherein the impurities are selected from the group consisting of calcium and strontium;
• and
• forming a plurality of transistors within the silicon substrate, wherein each transistor includes a source region and a drain region.