# US 5,440,268 A · AFC circuit for QPSK demodulator

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- Number: US 5,440,268 A
- Document ID: US5440268A
- Status: Granted
- Kind: A
- Application number: 08/306,957
- Filed: 1994-09-16
- Granted: 1995-08-08
- Earliest claimed: 1993-09-16
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Noboru Taga; Tatsuya Ishikawa; Susumu Komatsu
- Web page: https://patentgrep.com/patent/US5440268A

## CPC

- H04L 27/2332: {using a non-coherent carrier}
- H04L 2027/0032: {at baseband and passband}
- H04L 2027/0055: {single phase}
- H04L 2027/0057: {quadrature phase}
- H04L 2027/0065: {Frequency error detectors (H04L2027/0067 takes precedence)}
- H04L 2027/0081: {between loops of different bandwidths}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is valid or not through a detection of an absolute sample value of the symbol intermediate timing so as to result a second validity signal, and valid frequency error extractor for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the local oscillator when the frequency error signal has been proved to be valid by the first and the second validity signals.

## Claims

### Claim 1

An AFC circuit for a QPSK demodulator comprising:
means for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator;
digital conversion means for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal;
frequency error detection means for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals;
first validity determining means for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal;
second validity determining means for determining whether the frequency error signal is valid or not through a detection of an absolute sample value of the symbol intermediate timing so as to result a second validity signal; and
valid frequency error extracting means for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the local oscillator when the frequency error signal has been proved to be valid by the first and the second validity signals.

### Claim 2 (depends on 1)

An AFC circuit for a QPSK demodulator as claimed in claim 1, wherein the second validity determining means has means for detecting a C/N (carrier to noise ratio) of the modulated input signal and means, if the C/N is lower than a prescribed level, for broadening the validity determination limits for the second validity signal based on the detected C/N.

### Claim 3

An AFC circuit for a QPSK demodulator comprising:
means for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator;
digital conversion means for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal;
frequency conversion means for converting frequencies through a complex multiplication of multiplying the digital outputs from the frequency conversion means with a frequency conversion carrier;
frequency error detection means for detecting a frequency error between the quadrature related frequency converted signals using a symbol timing sample value and a symbol intermediate timing sample value in the frequency converted signals;
first validity determining means for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal;
second validity determining means for determining whether the frequency error signal is valid or not through a detection of an absolute sample value of the symbol intermediate timing so as to result a second validity signal; and
valid frequency error extracting means for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the local oscillator when the frequency error signal has been proved to be valid by the first and the second validity signals,
valid frequency error extracting means for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the frequency conversion carrier when the frequency error signal has been proved to be valid by the first and the second validity signals.

### Claim 4 (depends on 3)

An AFC circuit for a QPSK demodulator as claimed in claim 3, wherein the second validity determining means has means for detecting a C/N of the modulated input signal and means, if the C/N is lower than a prescribed level, for broadening the validity determination limits for the second validity signal based on the detected C/N.