External interface for a high performance graphics adapter allowing for graphics compatibility

An interface for interfacing a host processor to a graphics system processor, comprising:

• a computer program operating on the host processor for generating memory addresses and pixels associated with the memory addresses;
• a memory address translator for translating the generated memory addresses into translated memory addresses recognized by the graphics system processor;
• and
• a first graphics controller for storing the pixels into memory locations defined by the translated memory addresses, the first graphics controller comprising
• a first hidden register undefined in VGA and XGA standards for storing a first pixel configuration value, the first hidden register being writable from the host processor only by executing a predetermined sequence of register instructions to thereby unlock the first hidden register,
• first pixel swapping means, responsive to the first pixel configuration value, for selectively swapping the pixels from Intel order to Motorola order and from Motorola order to Intel order, and
• first pixel storing means for storing the swapped pixels into the memory locations.

An interface for interfacing a host processor to a graphics system processor, comprising:

• a computer program operating on the host processor for generating memory addresses and data elements associated with the memory addresses;
• a memory address translator for translating the generated memory addresses into translated memory addresses recognized by the graphics system processor, the memory address translator comprising
• a plurality of VGA registers for storing VGA control information;
• a plurality of XGA registers for storing XGA control information;
• a plurality of hidden registers undefined in VGA and XGA standards for storing translation state data, the hidden registers being writable from the host processor only by executing a predetermined sequence of register instructions to thereby unlock each hidden register;
• an address multiplexer having inputs for receiving the generated memory addresses, a State Save/Restore Data Port address, a plurality of Index Register addresses, and a plurality of memory mapped register addresses, and an output for providing the translated memory addresses as a function of said inputs;
• and
• a controller, responsive to the translation state data, the VGA control information and the XGA control information, for controlling the address multiplexer;
• a graphics controller for storing the data elements into memory locations defined by the translated memory addresses;
• and
• a back-end gate array including a serializer for reading the stored data elements and performing a parallel-serial conversion of the data elements in units of designated pixel size.

In a computer system comprising a host processor, a coprocessor, and memory at least partially addressable by both the host processor and the coprocessor through a common bus, a method for interfacing an operating system operating on the host processor with the coprocessor, the interface method comprising the steps of:

• a) defining a hidden register undefined in VGA and XGA standards at an I/O location on the common bus, the hidden register being accessible only by executing a predetermined sequence of register instructions on the host processor;
• b) writing a data value indicating a particular address translation mode from the host processor into the hidden register;
• c) writing XGA control data into an XGA register accessible on the common bus;
• d) reading the values from the hidden register and the XGA register;
• e) translating memory addresses generated by the operating system into translated memory addresses recognized by the coprocessor using a translation scheme determined by the values read from the hidden register and the XGA register;
• and
• f) storing data elements generated by the operating system into memory locations corresponding to the translated memory addresses.

In a computer system comprising a host processor, a coprocessor and memory at least partially addressable by both the host processor and the coprocessor through a common bus, an interface for interfacing an operating system on the host processor with the coprocessor, the interface comprising:

• means for translating memory addresses generated by the operating system into translated memory addresses recognized by the coprocessor;
• means for storing data elements generated by the operating system into the translated memory addresses, and
• means for detecting access to a translation lookaside buffer (TLB) by the host processor and informing the coprocessor of the detection, the means for detecting access comprising
• an address latch, coupled to the common bus, for latching memory addresses transmitted by the host processor on the common bus;
• source and destination address registers for storing source and destination addresses corresponding to a memory area undergoing a block data transfer by the coprocessor;
• an address comparator for comparing each of the latched addresses with the source and destination addresses and producing a coincidence signal thereby when any latched address falls within a predetermined proximity to the memory area undergoing the block data transfer;
• and
• interrupt generation means for producing the interrupt signal in response to the coincidence signal.

In a computer system comprising a host processor, a coprocessor having a non-Industry Standard Architecture (ISA) memory cycle, and memory at least partially addressable by both the host processor and the coprocessor through a common bus having an ISA memory cycle, an interface for interfacing an operating system operating on the host processor with the coprocessor, the interface comprising:

• means for translating memory addresses generated by the operating system into translated memory addresses recognized by the coprocessor:
• means for storing data elements generated by the operating system into the translated memory addresses;
• a bus master arbitrator for arbitrating occupation and release of the common bus between the host processor and the coprocessor;
• and
• means for converting memory cycles of the coprocessor to ISA memory cycles,
• wherein the means for converting comprises a coprocessor-to-bus converter, coupled between the coprocessor and the common bus, for delaying coprocessor read/write control signals and outputting thereby bus memory command signals onto the common bus in accordance with ISA timing requirements.

An interface for interfacing a host processor to a graphics system processor, comprising:

• a computer program operating on the host processor for generating memory addresses and data elements associated with the memory addresses;
• a memory address translator for translating the memory addresses into translated memory addresses recognized by the graphics system processor;
• a graphics controller for storing the data elements into the translated memory addresses;
• and
• a translation lookaside buffer (TLB) snoop logic circuit for detecting access to a TLB by the host processor and for informing the graphics system processor of the detection, the TLB snoop logic circuit including means for generating an interrupt signal for the graphics system processor in response to the detection, wherein the host processor and graphics system processor share a common bus, and wherein the TLB snoop logic circuit comprises
• an address latch, coupled to the common bus, for latching memory addresses transmitted by the host processor on the common bus;
• source and destination address registers for storing source and destination addresses respectively corresponding to memory areas undergoing a block data transfer by the graphics system processor;
• an address comparator for comparing each of the latched addresses with the source and destination addresses and producing a coincidence signal thereby when any latched address falls within a predetermined proximity to one of the memory areas undergoing the block data transfer;
• and
• interrupt generation means for interrupting the graphics system processor in response to the coincidence signal.

In a computer system comprising a host processor, a coprocessor, and memory at least partially addressable by both the host processor and the coprocessor through a common bus, a method for interfacing an operating system operating on the host processor with the coprocessor, the interface method comprising the steps of:

• a) translating memory addresses generated by the operating system into translated memory addresses recognized by the coprocessor;
• b) storing data elements generated by the operating system into the translated memory addresses;
• c) detecting access to a translating lookaside buffer (TLB) by the host processor and informing the coprocessor of the detection;
• and
• d) generating an interrupt signal for the coprocessor in response to the detection, wherein step c) comprises the steps of:
• i) latching a memory address transmitted by the host processor on the common bus;
• ii) reading source and destination addresses from source and destination address registers, the source and destination addresses respectively corresponding to a memory area undergoing a block data transfer by the coprocessor;
• and
• iii) comparing the latched address with the source and destination addresses and producing a detection signal thereby when the latched address falls within a predetermined proximity to the memory area undergoing the block data transfer.

An interface for interfacing a host processor to a graphics system processor, comprising:

• a computer program operating on the host processor for generating memory addresses and pixels associated with the memory addresses;
• a memory address translator for translating the generated memory addresses into translated memory addresses recognized by the graphics system processor;
• a first graphics controller for storing the pixels into memory locations defined by the translated memory addresses, the first graphics controller comprising
• a first hidden register for storing a first pixel configuration value, the first hidden register being writable from the host processor only by executing a predetermined sequence of register instructions to thereby unlock the first hidden register,
• first pixel swapping means, responsive to the first pixel configuration value, for selectively swapping the pixels from Intel order to Motorola order and from Motorola order to Intel order, and
• first pixel storing means for storing the swapped pixels into the memory locations;
• a translation lookaside buffer (TLB) snoop logic circuit for detecting access to a TLB by the host processor and for interrupting the graphics system processor in response thereto;
• a second graphics controller for storing the pixels into memory locations defined by the translated memory addresses, the second graphics controller comprising
• a second hidden register for storing a second pixel configuration value, the second hidden register being writable from the host processor only by executing a predetermined sequence of register instructions to thereby unlock the second hidden register,
• second pixel swapping means, responsive to the second pixel configuration value, for selectively swapping the pixels from Intel order to Motorola order and from Motorola order to Intel order, and
• second pixel storing means for storing the swapped pixels into the memory locations;
• wherein the first and second graphics controllers store first and second portions, respectively, of each pixel into the memory location defined by the translated memory address.