US 5,434,997 A · Method and apparatus for testing and debugging a tightly coupled mirrored processing system · patentgrep

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Abstract

A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

Claims19

Dependent claims

A computer system which includes tightly coupled mirrored CPUs for design debug and testing purposes, comprising:

a host bus having address, data and control portions;
clock signal generating means which generates a clocking signal used by said computer system;
memory coupled to said host bus for storing instructions and data that can be presented onto said host bus;
a master CPU coupled to said host bus which reads instructions and data from said memory using said host bus, executes instructions, writes data to said memory using said host bus and presents control signals onto said host bus during read and write operations;
a slave CPU coupled to said host bus which identically mirrors said data and instruction reads of said master CPU and identically mirrors instruction execution of said master CPU, wherein when said master CPU writes data onto said host bus, said slave CPU also generates write data, and wherein said slave CPU generates control signals during read and write cycles when said master CPU presents said control signals onto said host bus, said slave CPU including:
write data comparison means which receives write data presented by said master CPU onto said host bus and also receives said slave CPU write data for comparing said master CPU write data with said slave CPU write data and for generating a mirror error signal indicative thereof;
control signal comparison means which receives said control signals presented by said master CPU onto said host bus and also receives said control signals generated by said slave CPU for comparing said master CPU control signals with said slave CPU control signals and for generating said mirror error signal;
and
clock disabling means coupled to said write data comparison means and to said control signal comparison means for disabling said clock signal generating means when said mirror error signal indicates that said master CPU write data does not equal said slave CPU write data and when said mirror error signal indicates that said master CPU control signals are not the same as said slave CPU control signals.

6 more elements

A computer system which includes tightly coupled mirrored CPUs for design debug and testing purposes, comprising:

a host bus having address, data and control portions;
clock signal generating means which generates a clocking signal used by said computer system;
memory coupled to said host bus for storing instructions and data that can be presented onto said host bus;
a master CPU coupled to said host bus which reads instructions and data from said memory using said host bus, executes instructions, and writes data to said memory using said host bus;
a slave CPU coupled to said host bus which identically mirrors said data and instruction reads of said master CPU and identically mirrors instruction execution of said master CPU, wherein when said master CPU writes data onto said host bus, said slave CPU also generates write data, said slave CPU including:
write data comparison means which receives write data presented by said master CPU onto said host bus and also receives said slave CPU write data for comparing said master CPU write data with said slave CPU write data and for generating a mirror error signal indicative thereof;
and
clock disabling means coupled to said write data comparison means for disabling said clock signal generating means when said master CPU write data does not equal said slave CPU write data, and wherein each of said master and slave CPUs further includes:
a processor;
and
distributed system peripheral (DSP) logic including processor ports and interrupt controller logic;
wherein said DSP logic in said master CPU is referred to as the master DSP and said DSP logic in said slave CPU is referred to as the slave DSP, the computer system further including:
an expansion bus coupled to said host bus;
common system peripheral (CSP) logic coupled to said host bus;
and
a third bus coupled between said CSP logic and each of said DSP logic, wherein said CSP logic broadcasts read and write operations to each of said DSPs using said third bus;
wherein said master DSP receives data from said third bus, performs operations, and writes data to said CSP logic using said third bus;
wherein said slave DSP identically mirrors said data receive operations of said master DSP and identically mirrors operation of said master DSP, wherein when said master DSP writes data onto said third bus, said slave DSP also generates write data, said slave DSP including:
third bus comparison means which receives write data presented by said master DSP onto said third bus and also receives said write data generated by said slave DSP for comparing said master DSP write data with said slave CPU write data and for generating said mirror error signal;
and
wherein said clock disabling means is further coupled to said third bus comparison means and disables said clock signal generating means when said mirror error signal indicates that said master DSP write data does not equal said slave DSP write data.

18 more elements

A computer system which includes tightly coupled mirrored CPUs for design debug and testing purposes, comprising:

a host bus having address, data and control portions;
clock signal generating means which generates a clocking signal used by said computer system;
memory coupled to said host bus for storing instructions and data that can be presented onto said host bus;
a master CPU coupled to said host bus which reads instructions and data from said memory using said host bus, executes instructions, and writes data to said memory using said host bus;
a slave CPU coupled to said host bus which identically mirrors said data and instruction reads of said master CPU and identically mirrors instruction execution of said master CPU, wherein when said master CPU writes data onto said host bus, said slave CPU also generates write data, said slave CPU including:
write data comparison means which receives write data presented by said master CPU onto said host bus and also receives said slave CPU write data for comparing said master CPU write data with said slave CPU write data and for generating a mirror error signal indicative thereof;
clock disabling means coupled to said write data comparison means for disabling said clock signal generating means when said mirror error signal indicates that said master CPU write data does not equal said slave CPU write data;
and
means for generating a synchronizing signal that is provided to the master and slave CPUs, said master and slave CPUs each further including:
a timer having an output which generates timing signals for its respective CPU, said timer including a clock input receiving said synchronizing signal, wherein said timers in said master and slave CPUs operate in lockstep according to said synchronizing signal.

7 more elements

A computer system which includes tightly coupled mirrored CPUs for design debug and testing purposes, comprising:

a host bus having address, data and control portions;
clock signal generating means which generates a clocking signal used by said computer system;
memory coupled to said host bus for storing instructions and data that can be presented onto said host bus;
a master CPU coupled to said host bus which reads instructions and data from said memory using said host bus, executes instructions, and writes data to said memory using said host bus;
a slave CPU coupled to said host bus which identically mirrors said data and instruction reads of said master CPU and identically mirrors instruction execution of said master CPU, wherein when said master CPU writes data onto said host bus, said slave CPU also generates write data, said slave CPU including:
write data comparison means which receives write data presented by said master CPU onto said host bus and also receives said slave CPU write data for comparing said master CPU write data with said slave CPU write data and for generating a mirror error signal indicative thereof;
clock disabling means coupled to said write data comparison means for disabling said clock signal generating means when said mirror error signal indicates that said master CPU write data does not equal said slave CPU write data;
an expansion bus coupled to said host bus;
devices coupled to said expansion bus which generate a plurality of interrupt requests;
and
interrupt receive means coupled to said expansion bus for receiving interrupt requests generated by said expansion bus devices and for providing said interrupt requests to said master and slave CPUs;
and
wherein said master and slave CPUs each further comprise:
a processor;
an interrupt controller which receives said interrupt requests from said interrupt receive means and provides an interrupt signal to said CPU's processor;
and
interrupt controller synchronization means including means coupled between said interrupt controller and said processor for synchronizing said interrupt signal provided to said processor to a clocking signal.

14 more elements

A computer system which includes tightly coupled mirrored CPUs for design debug and testing purposes, comprising:

a host bus having address, data and control portions;
memory coupled to the host bus for storing instructons and data that can be presented onto said host bus;
a master CPU coupled to said host bus which reads instructions and data from said memory using said host bus, executes instructions, and writes data to said memory using said host bus;
a slave CPU coupled to said host bus which identically mirrors said data and instruction reads of said master CPU and identically mirrors instruction execution of said master CPU, wherein when said master CPU writes data onto said host bus, said slave CPU also generates write data;
comparing means coupled to said master CPU and said slave CPU for comparing certain operations of said master CPU and slave CPU and for generating a signal indicative thereof;
and
means for generating a synchronizing signal that is provided to the master and slave CPUs, and
wherein said master and slave CPUs each further include:
a timer having an output which generates timing signals for its respective CPU, said timer including a clock input receiving said synchronizing signal, wherein said timers in said master and slave CPUs operate in lockstep according to said synchronizing signal.

6 more elements

A computer system which includes tightly coupled mirrored CPUs for design debug and testing purposes, comprising:

a host bus having address, data and control portions;
memory coupled to the host bus for storing instructons and data that can be presented onto said host bus;
a master CPU coupled to said host bus which reads instructions and data from said memory, executes instructions, and writes data to said memory using said host bus;
a slave CPU coupled to the host bus which identically mirrors said data and instruction reads of said master CPU and identically mirrors instruction execution of said master CPU, wherein when said master CPU writes data onto said host bus, said slave CPU also generates write data;
comparing means coupled to said master CPU and said slave CPU for comparing certain operations of said master CPU and slave CPU and for generating a signal indicative thereof;
an expansion bus coupled to said host bus;
devices coupled to said expansion bus which generate a plurality of interrupt requests;
and
interrupt receive means coupled to said expansion bus for receiving interrupt requests generated by said expansion bus devices and for providing said interrupt requests to said master and slave CPUs;
and
wherein said master and slave CPUs each further comprise:
a processor;
an interrupt controller which receives said interrupt requests from said interrupt receive means and provides an interrupt signal to said CPU's processor;
and
interrupt controller synchronization means including means coupled between said interrupt controller and said processor for synchronizing said interrupt signal provided to said processor to a clocking signal.

12 more elements

Dependencies are inferred from the claim text.