US 5,434,899 AGranted

Phase clocked shift register with cross connecting between stages

AssigneeThomson Consumer Electronics, Inc.

InventorsRuquiya I. A. Huq, Sherman Weisbrod

Life of this patent

Estimating the term…

Loading patent…

Abstract

A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. The input transistor switch charges a capacitance associated with a control electrode of a switched pull-up output transistor. The voltage in the capacitance conditions the output transistor for generating an output pulse when subsequently a clock signal occurs to the output transistor. A clamping transistor discharges the capacitance in a manner to prevent further generation of the output pulse when subsequent pulses of the clock signal occur. The clamping transistor is responsive to an output pulse of a stage downstream in the chain. An impedance that is developed at the control electrode is substantially higher after the clamping operation occurs and remain high for most of the vertical interval.

Claims12

Dependent claims

A shift register, comprising:

means for generating a plurality of phase shifted clock signals;
and
a plurality of cascaded stages, a given one of said cascaded stages, including:
an output transistor responsive to a first clock signal of said clock signals for generating an output pulse at an output of said given stage;
an input switching means responsive to an output pulse developed at an output of a second of said cascaded stages when a clock signal applied thereto that is phase shifted with respect to said first clock signal occurs for generating a control signal that is stored on a capacitance that is coupled to a control electrode of said output transistor in said given stage, said control signal conditioning said output transistor for generating said output pulse of said given stage when said first clock signal occurs;
and
a clamping transistor having a conduction path coupled to said control electrode of said output transistor and being responsive at its control electrode to an output pulse developed at an output of a stage of said cascaded stages when a clock signal that is phase shifted with respect to said first clock signal occurs for clamping said control signals in said given stage to a level that prevents said output transistor from generating an output pulse when a following pulse of said first clock signal occurs, such that, after said signal is clamped, said clamping transistor develops an impedance in said control electrode of said output transistor that is substantially higher than when said signal is clamped.

4 more elements

A scanning register comprising:

a source of a plurality of clock signals of different phases;
a cascade connection of register stages, wherein clock signals of successive phase are cyclically coupled to successive register stages and wherein each stage comprises:
an input terminal coupled to an output terminal of an adjacent prior register stage and an output terminal coupled to an input terminal of an adjacent following register stage;
a source follower amplifier having supply terminals coupled to a respective clock signal, said source follower amplifier including the serial connection of a transistor and an impedance coupled across said supply terminals, said register stage output terminal formed by an interconnection of said transistor and said impedance, and having an input connection at a control electrode of said transistor;
and
an input stage having an output coupled to the input connection of said source follower amplifier and an input coupled to said input terminal, said input stage including an active device for unidirectionally conducting current between said transistor, and a further transistor having a principal conduction path coupled between said control electrode of said transistor and a potential sufficient to render said transistor non conductive, said further transistor having a control electrode connected to an output terminal of a following register stage in said cascade connection.

3 more elements

Dependencies are inferred from the claim text.