Flash EEPROM system cell array with more than two storage states per memory cell

In an array of a plurality of electrically erasable and programmable read only memory cells wherein each cell includes a split-channel field effect transistor that has in a semiconductor substrate a source and drain separated by a channel region, a floating gate positioned over only a first portion of and insulated from the channel region adjacent the drain, and a control gate extending over and insulated from the floating gate and a second portion of the channel adjacent the source, the first portion of said transistor having an effective threshold voltage resulting from a combination of a natural threshold voltage and a voltage responsive to a controllable level of charge on the floating gate, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, and the second portion of said transistor being connected in series with said first portion and having a conductance determined by a voltage on said control gate, a system for erasing, programming and reading the memory state of the cells in said array, comprising:

• means operably connected to said array for addressing a selected one or group of the plurality of memory cells,
• erasing means operably connected to said array for driving the effective threshold voltage of an addressed cell or group of cells to a base level by altering the charge on each addressed cell's floating gate,
• programming means operably connected to said array for altering the charge on the floating gate of an addressed cell until its said effective threshold voltage is substantially equal to one of a plurality of effective threshold voltage levels in excess of two corresponding to a plurality of individual detectable states in excess of two, whereby each cell of the array is programmable into one of said detectable states,
• reading means operably connected to said array for determining the amount of current that flows in an addressed cell, whereby the state of an addressed cell is determined from its measured current level, and
• wherein said natural threshold voltage is established at a level of at least three volts.

A memory system formed of an array of split-channel EEPROM cells, wherein individual cells comprise:

• source and drain regions formed in said substrate surface and separated by a channel region divided into first and second adjacent portions,
• a control gate positioned adjacent said source region and extending across the first portion of said channel region with a first gate dielectric layer therebetween in a manner to control conduction through the first channel portion in accordance with a level of voltage applied to the control gate, thereby forming a first transistor characterized by a fixed threshold in response to a voltage applied to the control gate,
• a floating gate positioned adjacent said drain region and extending across the second portion of said channel region with a second gate dielectric layer therebetween in a manner to control conduction through the second channel portion in accordance with a level of electronic charge stored thereon, said control gate also extending over at least a portion of the floating gate and being insulated therefrom, thereby forming a second transistor having a threshold level in response to a voltage applied to the control gate that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, and
• an erase gate positioned adjacent the floating gate with a tunnel dielectric layer therebetween,
• and wherein the system additionally comprises means operably connectable with at least said source, said drain, said control gate and said erase gate of an addressed one or more of the cells within the array for programming and reading any one of more than two programmable threshold states of the second transistor of said addressed one or more cells that results from any respective one of more than two levels of net charge being placed onto the floating gate, said second transistor given threshold level being established sufficiently high so that a majority of said more than two programmable threshold states result from a net positive charge on the floating gate.

For an array of electrically alterable memory cells having means for addressing individual cells to read and alter their states, each cell including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of altering a memory state of an addressed cell of the array, comprising the steps of:

• establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the cell in excess of two,
• presetting the effective threshold voltage of the addressed cell to a predetermined level by altering the amount of charge on the floating gate,
• setting the addressed cell to one of its said plurality of states by altering the amount of charge on the floating gate until its effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels, and
• wherein said given threshold voltage level is established to be at least three volts.

For a system containing an array of electrically alterable memory cells partitioned into a plurality of distinct blocks of cells and having means for addressing individual cells within said blocks to read and alter their states, each cell including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of operating said memory system, comprising the steps of:

• establishing (a) a plurality of effective memory cell threshold voltage levels in excess of two that correspond to a plurality of individually detectable memory cell states in excess of two, and (b) an effective base memory cell threshold voltage level,
• providing redundant cells for substitution in place of any bad cells within said blocks of memory cells,
• simultaneously altering the amount of charge on the floating gates of the memory cells within at least one of said blocks of cells toward said effective base threshold voltage level, thereby to preset the effective threshold voltage thereof,
• altering the amount of charge on the floating gate of at least one of the memory cells within said at least one of said blocks of cells in order to move its effective threshold voltage toward a desired one of said plurality of effective threshold voltage levels, thereby to set said at least one of the memory cells to one of said plurality of detectable states,
• generating addresses of any cells within said at least one of said blocks of cells that are not altered to a desired effective threshold voltage level, and
• wherein the setting step includes substituting at least one of said redundant cells for any of said at least one of the memory cells whose addresses have been so generated.

For an array of electrically alterable memory cells divided into blocks of cells and having means for addressing individual cells within said blocks to read and alter their states, said memory cells individually including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of operating the array, comprising the steps of:

• establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of detectable states of the individual cells in excess of two,
• setting the effective threshold voltage level of each of a plurality of cells addressed within one of said blocks to one of said plurality of levels by altering the amount of charge on the floating gate of said each of the plurality of cells until the cell's effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels, whereby the states of said plurality of addressed cells are individually set to one of said plurality of states,
• designating as a redundant block at least one of said blocks of cells other than said one of said blocks, and
• substituting said redundant block of cells for said one of said blocks, whereby a plurality of cells within said redundant block of cells become addressable for setting their effective threshold voltage levels to one of said plurality of levels.