ECL-to-BICOMS/CMOS translator

An ECL-to-BiCMOS/CMOS translator, comprising:

• an output stage having an output node for outputting a BiCMOS/CMOS level signal, the output stage further having a first bipolar transistor for coupling the output node to a first voltage supply and a second bipolar transistor for coupling the output node to a second voltage supply;
• a first input stage, responsive to a first one of a pair of differential ECL signals, for activating the first bipolar transistor of the output stage, the first input stage having a first P-channel transistor for coupling a first resistive element between the first voltage supply and the output node of the output stage;
• and
• a second input stage, responsive to a second one of the pair of differential ECL signals, for activating the second bipolar transistor of the output stage, the second input stage having a second P-channel transistor for coupling a second resistive element between the first voltage supply and the second voltage supply.

An ECL-to-BiCMOS/CMOS translator, comprising:

• an ECL receiver means for receiving a single ECL signal and for generating a pair of differential ECL signals in response thereto;
• an output stage having an output node for outputting a BiCMOS/CMOS level signal, the output stage further having a first bipolar transistor for coupling the output node to a first voltage supply and a second bipolar transistor for coupling the output node to a second voltage supply;
• a first input stage for activating the first bipolar transistor of the output stage, the first input stage having a first P-channel transistor having its source connected to the first voltage supply, its drain connected to the base of the first bipolar transistor of the output stage, and its gate connected to a first one of the pair of differential ECL signals, the first input stage further having a resistive element connected between the drain of the first P-channel transistor and the output node of the output stage;
• and
• a second input stage for activating the second bipolar transistor of the output stage, the second input stage having a second P-channel transistor having its source-connected to the first voltage supply, its drain connected to the base of the second bipolar transistor of the output stage, and its gate connected to a second one of the pair of differential ECL signals, the second input stage further having a resistive element connected between the drain of the second P-channel transistor and the second voltage supply.

An ECL-to-BiCMOS/CMOS translator, comprising;

• an ECL receiver stage for generating a pair of differential ECL signals, the ECL receiver stage being connectable to a first voltage supply and to a second voltage supply having a lower voltage potential than the first voltage supply, the differential ECL signals each having a logic high value that has a lower voltage potential than the first voltage supply and a logic low value that has a higher voltage potential than the second voltage supply;
• an output stage having an output node for outputting a BiCMOS/CMOS level signal, the output stage further having a first bipolar transistor for coupling the output node to a third voltage supply and a second bipolar transistor for coupling the output node to a fourth voltage supply;
• a first input stage, responsive to a first one of the pair of differential ECL signals, for activating the first bipolar transistor of the output stage, the first input stage having a first field effect transistor for coupling a first resistive element between the third voltage supply and the output node of the output stage;
• and
• a second input stage, responsive to a second one of the pair of differential ECL signals, for activating the second bipolar transistor of the output stage, the second input stage having a second field effect transistor for coupling a second resistive element between the third voltage supply and the fourth voltage supply.