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US 5,434,095 AGranted
Method for controlling electrical breakdown in semiconductor power devices
AssigneeSundstrand Corporation
InventorTheodore G. Hollinger
Life of this patent
Estimating the term…
Abstract
A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.
Claims4
A method for fabricating a vertical power-MOS transistor, comprising:
- providing a silicon substrate for fabricating a MOS transistor having a top surface;
- forming an island over a part of the silicon surface with a first dopant type;
- implanting a dopant of the same type residing in the island into the silicon on adjacent sides of the island;
- simultaneously diffusing the dopant on adjacent sides of the island further into the silicon to form first and second channel regions on opposite adjacent sides of the island and driving the dopant from the island down into the substrate to form a subregion in the silicon below the island, the subregion electrically connecting the adjacent channel regions to reduce the tendency for electrical breakdown in the transistor.
1 more element
A method for controlling electrical breakdown in a vertical power-MOS transistor, comprising:
- providing a power-MOS transistor having a set of associated channels with a given dopant type and a gate contact area, the gate contact area having an expanse thereunder that is at least partially bounded by said channels;
- electrically connecting the channels to reduce the build-up and concentration of electrical fields which tend to cause electrical breakdown.
Dependencies are inferred from the claim text.