Digital data receiver having DC offset cancelling preamplifier and dual-mode transimpedance amplifier

A transimpedance amplifier comprising:

• a first emitter-coupled transistor pair having a first transistor for operating on a data output signal and a second transistor for operating on a reference signal;
• a first Darlington-coupled, emitter-follower transistor pair coupled to respond to an output of the first transistor of the first emitter-coupled transistor pair for coupling an amplified output through a first feedback resistor to the first transistor of the first emitter-coupled transistor pair;
• a second Darlington-coupled, emitter-follower transistor pair coupled to respond to an output of the second transistor of the first emitter-coupled transistor pair;
• a peak hold capacitor;
• a second emitter-coupled transistor pair having a first transistor connected to respond to a voltage developed in said peak hold capacitor, and a second transistor connected to respond to an output of the second Darlington-coupled, emitter-follower transistor pair, said first and second emitter-coupled transistor pairs having dc operating points which are matched to each other;
• a current switching transistor connected to respond to an output of the second Darlington-coupled, emitter-follower transistor pair for charging said peak hold capacitor;
• and
• a buffer transistor for coupling the voltage developed in said peak hold capacitor through a second feedback resistor to said second transistor of the first emitter-coupled transistor pair as said reference signal.

A pre-amplifier circuit comprising:

• a pre-amplifier for receiving a digital data input signal and a correction signal and producing therefrom a data output signal, said pre-amplifier having a pair of output terminals for producing complementary output signals;
• low-level detector means connected to said pre-amplifier for producing a low-level signal representative of a minimum level of said digital data input signal during the time said data input signal is absent or less than a peak amplitude of the digital data input signal;
• and
• comparator means having a first input for receiving said low-level signal and a second input for receiving a reference voltage and detecting a difference between said low-level signal and said reference voltage and producing therefrom said correction signal to cause said pre-amplifier to cancel dc offset which may be contained in said digital data input signal,
• wherein said low-level detector means comprises:
• differential-input and differential-output booster amplifier means connected to the output terminals of said pre-amplifier having differential outputs;
• a peak detector having an input and an output, the output of the peak detector being connected to the first input of said comparator means;
• a buffer amplifier having an input and an output, the output of the buffer amplifier being connected to the second input of said comparator means;
• and
• means for coupling one of the differential outputs of the booster amplifier means to the input of said peak detector and coupling the other differential output of the booster amplifier means to the input of the buffer amplifier for causing said peak detector to produce said low-level signal and causing said buffer amplifier to produce said reference voltage so that said buffer amplifier and said peak detector have dc operating characteristics which are matched to each other and said reference voltage is substantially equal to an output voltage generated by said booster amplifier means when a difference between input voltages of said booster amplifier means is substantially zero.