Differential analog memory cell and method for adjusting same
AssigneeElantec, Inc.
InventorBruce D. Rosenthal
Life of this patent
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AssigneeElantec, Inc.
InventorBruce D. Rosenthal
Estimating the term…
A differential analog memory cell provides output signals governed by precisely adjustable voltage levels having minimal drift. The memory cell comprises a pair of differentially connected floating gate MOSFETs, each MOSFET having its source connected to a common current source and its drain connected to one leg of a current mirror. The floating gate of each MOSFET is connected to one electrode of a tunneling capacitor and one electrode of a coupling capacitor. Voltages applied to the other electrode of the tunneling capacitor inject charges onto the corresponding floating gate, the voltage of which is determined by the size of the coupling capacitor. Output voltages taken from the drains of the floating gate MOSFETs can be precisely adjusted up or down by applying single polarity voltage pulses to one or the other injector nodes.
A differential analog memory cell for precisely correcting offsets and adjusting bias levels in a circuit, the differential analog memory cell comprising:
The differential analog memory cell of claim 2, wherein the drain of each differentially connected MOSFETs is coupled to one leg of a current mirror, to form a differential amplifier.
An operational amplifier having a differential analog memory cell adjustable through a pair of voltage inputs for correcting the offset of the amplifier output voltage, the operational amplifier comprising:
A method for precisely adjusting the charge on a differential analog cell comprising differentially connected floating gate MOSFETs, the method comprising the steps of:
Dependencies are inferred from the claim text.