VDMOS transistor with improved breakdown characteristics

A microelectronic power device structure, comprising:

• at least one matrix of source cells at a first surface of a monolithic semiconductor chip, each comprising a source diffusion, a body region substantially enclosing and having a conductivity type which is opposite to that of said source diffusion, and a gate capacitively coupled to a surface edge of said source diffusion;
• a field-isolation dielectric layer alongside said matrix;
• and
• a field-plate structure overlying an edge portion of said field-isolation dielectric layer facing peripheral ones of said matrix of source cells;
• a field-isolation diffusion, having the same conductivity type as said body regions, lying under said field-isolation dielectric layer, along the edge thereof facing said peripheral cells;
• an electrical connection between said field-isolation diffusion and a source region of the transistor;
• and
• a drain region, of the same conductivity type as said source region, and electrically connected to a second surface of said monolithic semiconductor chip, opposite said first surface.

A VDMOS transistor comprising:

• at least one matrix of source cells, each comprising a source diffusion, a body region substantially enclosing and having a conductivity type which is opposite to that of said source diffusion, and a gate capacitively coupled to a surface edge of said source diffusion;
• a drain diffusion having the same conductivity type as said source diffusion, and underlying said source and body regions, and being separated therefrom by a drift region having the same conductivity type as said drain diffusion;
• a field-isolation dielectric layer alongside said matrix;
• and
• a field-plate structure overlying an edge portion of said field-isolation layer facing peripheral ones of said matrix of source cells;
• a field-isolation diffusion, having the same conductivity type as said body region, lying under said field-isolation dielectric layer, along the edge thereof facing said peripheral cells;
• an electrical connection between said field-isolation diffusion and a source region of the transistor.

An integrated VDMOS transistor comprising:

• at least one matrix of source cells, each including a respective source region and a respective body region substantially enclosing and having a conductivity type which is opposite to that of said source diffusion, in a continuous monocrystalline layer;
• a drain-connection diffusion;
• and
• a first buried layer portion, lying beneath and having the same conductivity type as said source diffusions, and ohmically connected to said drain-connection diffusion;
• a field-isolation diffusion, having a second conductivity type, and lying under a strip of a field-isolation dielectric layer separating said matrix of cells from said drain-connection diffusion;
• and
• a biplanar field-plate overlaying an edge portion of said field-isolation dielectric layer facing peripheral cells of said matrix,
• and wherein said field-isolation diffusion under said edge portion of the field-isolation dielectric layer, topped by said field-plate, is electrically connected to a source region of the transistor through a projection of a body region of at least one of said peripheral source cells of said matrix extending toward the edge of said field-isolation dielectric layer and intersecting said field-isolation diffusion present under the edge of said field-isolation layer.