Latent defect handling in EEPROM devices

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting word line defects in the EEPROM memory array comprising the steps of:

• providing a memory controller for controlling memory operations of said memory device;
• providing a word line leakage detector within said memory device;
• establishing under the control of said memory controller a predetermined potential difference for a word line under test relative to the substrate and a set of access lines that are capable of being shorted to said word line under test;
• using said word line leakage detector under the control of said memory controller to detect a short circuit condition at said word line under test when a leakage current measured therein exceeded a predetermined level;
• and
• repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every word line to be tested in the EEPROM memory array.

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting word line defects in the EEPROM memory array comprising the steps of:

• providing a memory controller for controlling memory operations of said memory device;
• establishing under the control of said memory controller a predetermined potential difference for a bit line under test relative to the substrate and a set of access lines that are capable of being shorted to said bit line under test;
• detecting under the control of said memory controller a short circuit condition at said bit line under test when a leakage current measured therein exceeded a predetermined level;
• and
• repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every bit line to be tested in the EEPROM memory array.

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting erase line defects in the EEPROM memory array comprising the steps of:

• providing a memory controller for controlling memory operations of said memory device;
• providing a erase line leakage line detector within said memory device;
• establishing under the control of said memory controller a predetermined potential difference for a erase line under test relative to the substrate and a set of access lines that are capable of being shorted to said erase line under test;
• using said erase line leakage detector under the control of said memory controller to detect a short circuit condition at said erase line under test when a leakage current measured therein exceeded a predetermined level;
• and
• repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every erase line to be tested in the EEPROM memory array.

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting defects in a specified type of access line in the EEPROM memory array comprising the steps of:

• providing a memory controller for controlling memory operations of said memory device;
• providing a leakage detector within said memory device
• establishing under the control of said memory controller a predetermined potential difference for an access line under test of said specified type relative to the substrate and a set of access lines that are capable of being shorted to said access line under test;
• using said leakage detector under the control of said memory controller to detect a short circuit condition at said access line under test when a leakage current measured therein exceeded a predetermined level;
• and
• repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every access line of said specified type to be tested in the EEPROM memory array.

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting column defects due to a bit line shorted to another type of access line in the EEPROM memory array, comprising the steps of:

• providing a memory controller for controlling memory operations of said memory device;
• powering under the control of said memory controller a pair of bit lines in a column under test to voltage conditions for reading while keeping all other bit lines in the EEPROM memory array floated and all word lines and erase lines grounded;
• detecting under the control of said memory controller a short circuit condition at said pair of bit lines under test when a leakage current measured therein exceeded a predetermined level;
• and
• repeating the steps of powering and detecting for the pair of bit lines in every column to be tested in the EEPROM memory array.

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting column defects due to bit line short circuit in the EEPROM memory array, comprising the steps of:

• providing a memory controller for controlling memory operations of said memory device;
• powering under the control of said memory controller a pair of bit lines in each column among a set of columns simultaneously under test to voltage conditions for reading while keeping all word lines grounded and all other bit lines floated;
• detecting under the control of said memory controller a short circuit condition at the pair of bit lines in each column among the set of columns simultaneously under test when a leakage current measured in the pair of bit lines exceeded a predetermined level;
• and
• repeating the steps of powering and detecting for every set of columns simultaneously under test in the EEPROM memory array.

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting column defects due to bit line short circuit in the EEPROM memory array, comprising the steps of:

• providing a memory controller for controlling memory operations of said memory device;
• maintaining at least one row of cells all pre-programmed to a memory state corresponding substantially to a minimum conduction current through the source and drain of each cell during a read operation;
• detecting under the control of said memory controller any short circuit condition at a column by reading the programmed memory state in each of said at least one row of cells therein and determining if the pair of bit lines in the column has a conduction current substantially more than said minimum current;
• and
• repeating the steps of reading and detecting for every column to be tested in the EEPROM memory array.

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting column defects due to bit line short circuit in the EEPROM memory array, comprising the steps of:

• providing a memory controller for controlling memory operations of said nenory device;
• maintaining at least one row of cells all pre-erased to a memory state corresponding to substantially a maximum conduction current through the source and drain of each cell during a read operation;
• detecting under the control of said memory controller any short circuit condition at a column by reading the programmed memory state in each of said at least one row of cells therein and determining if the pair of bit lines in the column has a conduction current substantially less than said maximum conduction current;
• and
• repeating the steps of reading and detecting for every column to be tested in the EEPROM memory array.

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said memory array being organized in a two-dimensional array and into sectors consisting of one or more rows of cells that are erasable together, the two-dimensional array being addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, another type of access line being erase lines connected to the erase electrodes of every cells in each sector, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for handling defects in the EEPROM memory array comprising providing a memory controller for controlling memory operations of said memory device, said memory controller performing the steps of:

• detecting any defective access line of the memory array by measuring therein a leakage current that exceeds a predetermined level;
• recovering the data from defective memory cells in said defective access line;
• mapping out the defective memory cells in said defective access line and replacing with substitute memory cells;
• replacing the recovered data in the substitute memory cells.