Method of fabricating a complementary heterojunction FET

A method of fabricating a complimentary heterojunction device comprising the steps of:

• providing a supporting substrate structure defining a supporting surface;
• forming a first semiconductive layer of material on the supporting surface of the substrate structure, the first semiconductive layer including a first layer of semiconductor material having a conduction band and a valence band, each with a predetermined energy level, and with a Fermi level in the valence band to cause the first semiconductive layer to have a first type of conductivity;
• forming a first barrier layer on the first semiconductive layer;
• forming a second semiconductive layer on the first barrier layer, the second semiconductive layer including a second layer of semiconductor material having a conduction band and a valence band, each with a predetermined energy level, and with a Fermi level in the conduction band to cause the second semiconductive layer to have a second type of conductivity opposite to the first type;
• forming a cap structure on the second semiconductive layer, the cap structure including a second barrier layer positioned on the second semiconductive layer, a first cap layer positioned on the second barrier layer and a second cap layer positioned on the first cap layer;
• selecting a first area for a first complimentary heterojunction FET of a first conductivity type,and forming a first gate electrode on the second cap layer to define a first conduction channel for the first heterojunction FET in the second semiconductive layer;
• etching the second cap layer of the cap structure, utilizing the first gate electrode as a mask, and forming a first source and a first drain electrode on opposite sides of the first gate electrode on the first cap layer, the second and first cap layers being selected to pin the Fermi level in the first conduction channel such that number of carriers in the first conduction channel are substantially less than number of carriers in surrounding portions of the second semiconductive layer, whereby the first source and first drain electrodes are electrically coupled to the first conduction channel and conduction between the first source and first drain electrodes in the first conduction channel is controllable by the first gate electrode;
• selecting a second area, spaced from the first area, for a second complimentary heterojunction FET of a second conductivity type different than the first conductivity type and forming a second gate electrode on the first cap layer;
• etching the first cap layer of the cap structure and the second barrier layer of the cap structure in the second area, utilizing the second gate electrode as a mask, and forming a second source and a second drain electrode on opposite sides of the gate electrode on the second semiconductive layer, the first cap layer being selected to pin the Fermi level in the second conduction channel such that number of carriers in the second conduction channel are substantially less than number of carriers in surrounding portions of the first semiconductive layer, whereby the second source and second drain electrodes are electrically coupled to the second conduction channel and conduction between the second source and second drain electrodes in the second conduction channel is controllable by the second gate electrode.