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US 5,426,328 AGranted
BICDMOS structures
AssigneeSiliconix Incorporated
InventorsHamza Yilmaz, Richard K. Williams, Michael E. Cornell, Jun W. Chen
Life of this patent
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Abstract
A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
Claims14
A method, comprising the step of:
- using an isolation structure to isolate an MOS transistor from a bipolar transistor, said isolation structure comprising:
- a buried isolation region extending downward into a substrate layer, said substrate layer being of a semiconductor material of a first conductivity type, said buried isolation region also extending upward into an epitaxial layer, said epitaxial layer being of a semiconductor material of a second conductivity type opposite said first conductivity type, said epitaxial layer having a thickness of at least approximately eight microns, said epitaxial layer being disposed over said substrate layer, said epitaxial layer having an upper surface, said buried isolation region having an upper surface disposed below said upper surface of said epitaxial layer, said buried isolation region being of a semiconductor material of said second conductivity type;
- a buried well region disposed only in said epitaxial layer, said buried well region extending upward from said upper surface of said buried isolation layer so that said buried well region is separated and electrically isolated from said substrate layer, said buried well region having an upper surface, said buried well region being of a semiconductor material of said first conductivity type;
- and
- a well region disposed in said epitaxial layer, said well region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said well region having a lower surface, said lower surface of said well region contacting said upper surface of said buried well region so that said well region is separated and electrically isolated from said substrate layer, said well region being of a semiconductor material of said first conductivity type,
- wherein said bipolar transistor is formed in said well region at said upper surface of said epitaxial layer, and wherein said MOS transistor is formed at said upper surface of said epitaxial layer but outside said well region.
3 more elements
An isolated well structure for containing a transistor, comprising:
- a substrate layer of a semiconductor material of a first conductivity type;
- an epitaxial layer of a semiconductor material of a second conductivity type opposite said first conductivity type, said epitaxial layer disposed over said substrate layer and having a thickness of at least approximately eight microns, said epitaxial layer having an upper surface;
- a buried isolation region extending downward into said substrate layer and also extending upward into said epitaxial layer, said buried isolation region having an upper surface disposed below said upper surface of said epitaxial layer, said buried isolation region being of a semiconductor material of said second conductivity type;
- a buried well region disposed only in said epitaxial layer, said buried well region extending upward from said upper surface of said buried isolation region so that said buried well region is separated and electrically isolated from said substrate layer, said buried well region having an upper surface, said buried well region being of a semiconductor material of said first conductivity type;
- and
- a well region disposed in said epitaxial layer, said well region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said well region having a lower surface, said lower surface of said well region contacting said upper surface of said buried well region so that said well region is separated and electrically isolated from said substrate layer, said well region being of a semiconductor material of said first conductivity type, said transistor being formed in said well region at said upper surface of said epitaxial layer.
3 more elements
A vertical transistor structure, comprising:
- a substrate layer of a semiconductor material of a first conductivity type;
- an epitaxial layer of a semiconductor material of a second conductivity type opposite said first conductivity type, said epitaxial layer disposed over said substrate layer and having a thickness of at least approximately eight microns, said epitaxial layer having an upper surface;
- a collector buried region extending downward into said substrate layer and also extending upward into said epitaxial layer, said collector buried region having an upper surface disposed below said upper surface of said epitaxial layer, said collector buried region being of a semiconductor material of said second conductivity type;
- a collector sinker region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said collector sinker region contacting said collector buried region, said collector buried region and said collector sinker region separating a collector portion of said epitaxial layer from other portions of said epitaxial layer and from said substrate layer, said collector sinker region being of a semiconductor material of slid second conductivity type;
- a base region disposed in said collector portion of said epitaxial layer, said base region extending downward into said collector portion of said epitaxial layer from said upper surface of said epitaxial layer, said base region being of a semiconductor material of said first conductivity type;
- a polysilicon layer disposed over said upper surface of slid epitaxial layer and being physically separated from said epitaxial layer;
- a base contact region disposed in said base region, said base contact region having an edge which is self-aligned with a first edge of said polysilicon layer, said base contact region being of a semiconductor material of said first conductivity type;
- and
- an emitter region disposed in said base region, said emitter region having an edge which is self-aligned with a second edge of said polysilicon layer, said emitter region being of a semiconductor material of said second conductivity type, said polysilicon layer being disposed substantially entirely between said base contact region and said emitter region in a lateral dimension.
6 more elements
Structure, comprising:
- a relatively high voltage lateral bipolar transistor capable of sustained operation at voltages up to approximately 60 volts;
- a relatively low voltage N-channel field effect transistor incapable of sustained operation at voltages above approximately 20 volts;
- and
- means;
- for isolating said relatively high voltage lateral bipolar transistor from said relatively low voltage N-channel field effect transistor, said means for isolating comprising a well region of a semiconductor material of a first conductivity type, a buried well region disposed entirely in an epitaxial layer and being of at semiconductor material of said first conductivity type, and a buried isolation region being of a semiconductor material of a second conductivity type opposite said first conductivity type, said buried isolation region extending upward into said epitaxial layer and contacting said buried well region, said buried isolation region also extending downward into a substrate layer, said epitaxial layer being at least approximately eight microns thick.
2 more elements
A method comprising the step of:
- using an isolation structure to isolate an MOS transistor from a bipolar transistor, said isolation structure comprising:
- a buried isolation region extending downward into a substrate layer, said substrate layer being of a semiconductor material of a first conductivity type, said buried isolation region also extending upward into an epitaxial layer, said epitaxial layer being of a semiconductor material of a second conductivity type opposite said first conductivity type, said epitaxial layer having a thickness of at least approximately eight microns, said epitaxial layer being disposed over said substrate layer, said epitaxial layer having an upper surface, said buried isolation region having an upper surface disposed below said upper surface of said epitaxial layer, said buried isolation region being of a semiconductor material of said second conductivity type;
- a buried well region disposed only in said epitaxial layer, said buried well region extending upward from said upper surface of said buried isolation layer so that said buried well region is separated and electrically isolated from said substrate layer, said buried well region having an upper surface, said buried well region being of a semiconductor material of said first conductivity type;
- and
- a well region disposed in said epitaxial layer, said well region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said well region having a lower surface, said lower surface of said well region contacting said upper surface of said buried well region so that said well region is separated and electrically isolated from said substrate layer, said well region being of a semiconductor material of said first conductivity type,
- wherein said bipolar transistor is formed in said well region at said upper surface of said epitaxial layer, and wherein said MOS transistor is formed at said upper surface of said epitaxial layer but outside said well region, said isolation structure further comprising a second buried well region of a semiconductor material of said first conductivity type, said second buried well region extending downward from said buried isolation region into said substrate layer, said second buried well region being separated from said buried well region by said buried isolation region.
3 more elements
An isolated well structure for containing a transistor, comprising:
- a substrate layer of a semiconductor material of a first conductivity type;
- an epitaxial layer of a semiconductor material of a second conductivity type opposite said first conductivity type, said epitaxial layer disposed over said substrate layer and having a thickness of at least approximately eight microns, said epitaxial layer having an upper surface;
- a buried isolation region extending downward into said substrate layer and also extending upward into said epitaxial layer, said buried isolation region having an upper surface disposed below said upper surface of said epitaxial layer, said buried isolation region being of a semiconductor material of said second conductivity type;
- a buried well region disposed only in said epitaxial layer, said buried well region extending upward from said upper surface of said buried isolation region so that said buried well region is separated and electrically isolated from said substrate layer, said buried well region having an upper surface, said buried well region being of a semiconductor material of said first conductivity type;
- a well region disposed in said epitaxial layer, said well region extending downward into said epitaxial layer from said Upper surface of said epitaxial layer, said well region having a lower surface, said lower surface of said well region contacting said upper surface of said buried well region so that said well region is separated and electrically isolated from said substrate layer, said well region being of a semiconductor material of said first conductivity type, said transistor being formed in said well region at said upper surface of said epitaxial layer;
- and
- a second buried well region of a semiconductor material of said first conductivity type extending downward from said buried isolation region into said substrate layer, said second buried well region being separated from said buried well region by said buried isolation region.
4 more elements
Dependencies are inferred from the claim text.