US 5,426,072 A · Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate

Abstract

A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

Claims24

Dependent claims

A method for fabricating a circuit assembly, comprising the steps of:

(a) providing a multilayered wafer having a first substrate, an electrically insulating dielectric oxide layer overlying a surface of the first substrate, and a layer of semiconductor material overlying the dielectric oxide layer;
(b) processing the semiconductor material layer to form at least one electrically conductive feedthrough through the semiconductor material layer and to form circuitry within the semiconductor material layer;
(c) forming interconnection means that overlie the semiconductor material layer and that are electrically coupled to the at least one feedthrough;
(d) attaching a temporary substrate such that the interconnection means are interposed between the semiconductor material layer and the temporary substrate;
(e) removing the first substrate, the step of removing including a step of etching the first substrate so as to expose the dielectric oxide layer;
and
(f) forming further interconnection means through the exposed dielectric oxide layer for electrically coupling at least to the at least one feedthrough, thereby fabricating a first circuit assembly.

4 more elements

A method for fabricating a three-dimensional integrated circuit assembly, comprising the steps of:

(a) providing a first multilayered wafer having a first substrate, an electrically insulating dielectric oxide layer overlying a surface of the first substrate, and a layer of semiconductor material overlying the dielectric oxide layer;
(b) processing the semiconductor material layer to form at least one electrically conductive feedthrough through the semiconductor material layer and to form circuitry as required within the semiconductor material layer;
(c) forming interconnection means that overlies the semiconductor material layer and that is electrically coupled to the at least one feedthrough;
(d) attaching the first wafer to a temporary substrate such that the interconnection means is interposed between the semiconductor material layer and the temporary substrate;
(e) removing the first substrate, the step of removing including a step of etching the first substrate so as to expose the dielectric oxide layer;
(f) forming further interconnection means through the exposed dielectric oxide layer for electrically contacting at least the at least one feedthrough, the step of forming further interconnection means resulting in a first circuit assembly that includes the processed semiconductor material layer, the interconnection means formed over a first major surface of the processed semiconductor material layer, and the further interconnection means formed over a second major surface of the processed semiconductor layer;
(g) coupling the further interconnection means to interconnection means of a second multilayered wafer, the second multilayered wafer including a supporting substrate disposed on a surface opposite to a surface that underlies the interconnection means of the second multilayered wafer;
and
(h) removing the temporary substrate from the first circuit assembly.

6 more elements

Dependencies are inferred from the claim text.

Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate

Life of this patent

Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate

Life of this patent

Abstract

Claims24