US 5,424,687 A · PLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillation

Abstract

According to an output from a voltage-controlled oscillator, there are generated by a fractional divider a high-frequency division signal and a low-frequency division number. A phase comparison is conducted between the high-frequency division signal and a high-frequency reference signal by a phase comparator. A phase comparison is carried out between the low-frequency division signal and a low-frequency reference signal by a phase comparator. Either one of the outputs from the phase comparators is selected by a selector to be fed to a filter, thereby producing a control voltage for the voltage-controlled oscillator. A high-resolution division is achieved by the fractional division; consequently, disturbance of the oscillation frequency due to a change-over of the selector is suppressed. There is obtained a PLL frequency synthesizer developing a high-speed lock-up and a highly stable oscillation.

Claims9

Dependent claims

A PLL frequency synthesizer in which a phase comparison is conducted between a reference signal and an oscillation signal to control a phase of the oscillation signal so as to produce an oscillation signal related to the reference signal, comprising:

reference signal dividing means for generating a first reference signal by dividing the reference signal and for generating a second reference signal by dividing the first reference signal by a predetermined division number;
fractional dividing means for dividing the oscillation frequency of the oscillation signal by a fractional division number and thereby producing a first division signal having a frequency substantially equal to that of the first reference signal and for producing a second division signal by dividing the first division signal by the predetermined division number;
first comparing means for comparing the first reference signal with the first division signal and thereby producing a first comparison signal;
second comparing means for comparing the second reference signal with the second division signal and thereby producing a second comparison signal;
and
selecting means for selecting according to a state of the first comparison signal either one of the first and second comparison signals, thereby controlling the phase of the oscillation signal according to the comparison signal created from the selecting means.

3 more elements

A PLL frequency synthesizing method in which a phase comparison is conducted between a reference signal and an oscillation signal to control a phase of the oscillation signal so as to produce an oscillation signal related to the reference signal, comprising:

a reference signal dividing step of generating a first reference signal by dividing the reference signal and for generating a second reference signal by dividing the first reference signal by a predetermined division number;
a fractional dividing step of dividing the oscillation frequency of the oscillation signal by a fractional division number and thereby producing a first division signal having a frequency substantially equal to that of the first reference signal and for producing a second division signal by dividing the first division signal by the predetermined division number;
a first comparing step of comparing the first reference signal with the first division signal and thereby producing a first comparison signal;
a second comparing step of comparing the second reference signal with the second division signal and thereby producing a second comparison signal;
and
a selecting step of selecting according to a state of the first comparison signal either one of the first and second comparison signals, thereby controlling the phase of the oscillation signal according to the comparison signal created from the selecting means.

3 more elements

Dependencies are inferred from the claim text.

PLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillation

Life of this patent

PLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillation

Life of this patent

Abstract

Claims9