Processing commands and data in a common pipeline path in a high-speed computer graphics system

A pipelined graphics processing system for sequentially processing a plurality of data blocks including only graphics data or pipeline setup and control commands and associated setup and control data, comprising:

• a graphics pipeline having at least two pipelined processing circuits which perform predetermined functions on data blocks input thereto, each pipelined processing circuit including means for reading predetermined bits of received data blocks and for processing graphics data and pipeline setup and control commands and associated setup and control data within read data blocks which said pipelined processing circuit is authorized to process;
• and
• means for providing data blocks having a predetermined number of bits to said graphics pipeline, each data block including means read by said reading means of each pipelined processing circuit for indicating whether that data block contains a pipeline setup and control command, each data block containing a pipeline setup and control command further comprising identifying means read by said reading means of each pipelined processing circuit for identifying whether said pipelined processing circuit is authorized to process that pipeline setup and control command, said providing means providing said pipeline setup and control commands in said data blocks in the desired order for processing by said pipelined processing circuits such that a pipeline data flush is not necessary between reconfigurations of said pipelined processing circuits.

A method of sequentially processing a plurality of data blocks including only system data or pipeline setup and control commands and associated setup and control data in a data processing pipeline having at least two pipelined processing circuits which perform predetermined functions on data blocks input thereto, each pipelined processing circuit including means for reading predetermined bits of received data blocks and for processing system data and pipeline setup and control commands and associated setup and control data within read data blocks which said pipelined processing circuit is authorized to process, comprising the steps of:

• inputting data blocks having a predetermined number of bits to a first of said pipelined processing circuits, said pipeline setup and control commands being provided in said data blocks in the desired order for processing by said pipelined processing circuits such that a pipeline data flush is not necessary between reconfigurations of said pipelined processing circuits;
• and
• for each pipelined processing circuit of said data processing pipeline, performing the steps of:
• said reading means determining whether an input data block contains a pipeline setup and control command, and, if the input data block contains a pipeline setup and control command, further determining whether the current pipelined processing circuit is authorized to process that pipeline setup and control command, and
• if the current pipelined processing circuit is authorized to process the pipeline setup and control command in the input data block, said processing means of the current pipelined processing circuit processing that pipeline setup and control command and passing results of the processing of that pipeline setup and control command to the next pipelined processing circuit in the data processing pipeline, but if the current pipelined processing circuit is not authorized to process the pipeline setup and control command in the input data block, said processing means passing the input data block containing the pipeline setup and control command through the current pipelined processing circuit unprocessed to the next pipelined processing circuit in the data processing pipeline.