Data processing system having selective data save and address translation mechanism utilizing CPU idle period

A data processing system comprising:

• a main memory having a plurality of divided storage areas;
• an auxiliary memory in which contents of said main memory are saved;
• first save means, connected to said main memory and said auxiliary memory, and including means for saving data from each storage area of said main memory into said auxiliary memory during a normal operation of said data processing system, and means for setting save end information for storage areas, from which data is saved into said auxiliary memory;
• update means, connected to said main memory, for, when data in said main memory is updated, resetting the save end information for the storage areas in which the updated data is stored;
• second save means, connected to said main memory and said auxiliary memory, for saving data in the storage areas for which the save end information is reset when said data processing system must be stopped;
• and
• wherein said first save means performs the save operation when a program status word indicates that the system is in a waiting state during performing a program.

A computer comprising;

• a main memory means for storing data in units of data blocks,
• an auxiliary memory;
• first save means, connected to said main memory means and said auxiliary memory, for saving the data stored in said main memory means into said auxiliary memory in units of data blocks during a normal operation of said computer, said first save means including a CPU for controlling said first save means during an idle state of the CPU;
• and
• second save means, connected to said main memory means and said auxiliary memory, and including means for detecting data blocks, of the data stored in said main memory means, which are not saved by said first save means, and data blocks including data which is updated after the data save operation is performed by said first save means, and means for saving the detected data blocks in said auxiliary memory, when stoppage of said computer is designated.