Phase lock loop with selectable frequency switching time

A phase lock loop (PLL) circuit for controlling an oscillator to provide an output signal which is phase-locked to a reference signal with high frequency stepping resolution and low phase locking time, said PLL circuit comprising:

• a comparator which receives first and second comparator signals at first and second comparator signal frequencies and phases, respectively, and which compares said first and second comparator signals and in accordance therewith provides a third comparator signal representing a phase difference between said first and second comparator signal phases;
• a filter, coupled to said comparator, which receives said third comparator signal, and which receives a dynamic filter control signal having active and inactive states and in accordance therewith filters said third comparator signal to provide a frequency control signal for controlling an oscillator to select a frequency of an output signal from said oscillator, wherein said third comparator signal is filtered in accordance with one of a plurality of filter bandwidths selected in accordance with said dynamic filter control signal;
• a reference converter, coupled to said comparator, which receives a reference source signal at a reference source signal frequency, and which receives a dynamic reference control signal having active and inactive states and in accordance therewith provides said first comparator signal, wherein said first comparator signal frequency is proportional to said reference source signal frequency in accordance with one of a plurality of reference proportionality factors selected in accordance with said dynamic reference control signal;
• and
• a feedback converter, coupled to said comparator, which receives said oscillator output signal at said oscillator output signal frequency, and which receives a dynamic feedback control signal having active and inactive states and in accordance therewith provides said second comparator signal, wherein said second comparator signal frequency is proportional to said oscillator output signal frequency in accordance with one of a plurality of feedback proportionality factors selected in accordance with said dynamic feedback control signal;
• wherein said selected ones of said pluralities of filter bandwidths, reference proportionality factors and feedback proportionality factors together correspond to one of a plurality of time intervals, and wherein said active states of said dynamic filter control signal, said dynamic reference control signal and said dynamic feedback control signal all coincide with one another.

A phase lock loop (PLL) method for controlling an oscillator to provide an output signal which is phase-locked to a reference signal with high frequency stepping resolution and low phase locking time, said PLL method comprising the steps of:

• receiving a reference source signal at a reference source signal frequency;
• receiving a dynamic reference control signal having active and inactive states and in accordance therewith selecting one of a plurality of reference proportionality factors;
• providing a first comparator signal at a first comparator signal frequency and phase, wherein said first comparator signal frequency is proportional to said reference source signal frequency in accordance with said selected one of said plurality of reference proportionality factors;
• receiving an oscillator output signal at an oscillator output signal frequency;
• receiving a dynamic feedback control signal having active and inactive state and in accordance therewith selecting one of a plurality of feedback proportionality factors;
• providing a second comparator signal at a second comparator signal frequency and phase, wherein said second comparator signal frequency is proportional to said oscillator output signal frequency in accordance with said selected one of said plurality of feedback proportionality factors;
• comparing said first and second comparator signals;
• providing a third comparator signal which represents a phase difference between said first and second comparator signal phases;
• receiving a dynamic filter control signal having active and inactive states and in accordance therewith selecting one of a plurality of filter bandwidths;
• filtering said third comparator signal in accordance with said selected one of said plurality of filter bandwidths to provide a frequency control signal for controlling an oscillator to select said frequency of said output signal from said oscillator;
• wherein said selected ones of said pluralities of filter bandwidths, reference proportionality factors and feedback proportionality factors together correspond to one of a plurality of time intervals, and wherein said active states of said dynamic filter control signal, said dynamic reference control signal and said dynamic feedback control signal all coincide with one another.